| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 1272 SDValue SubVec = N->getOperand(1); in SplitVecRes_INSERT_SUBVECTOR() local
1279 EVT SubVecVT = SubVec.getValueType(); in SplitVecRes_INSERT_SUBVECTOR()
1289 Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, LoVT, Lo, SubVec, Idx); in SplitVecRes_INSERT_SUBVECTOR()
1297 Hi = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, Hi.getValueType(), Hi, SubVec, in SplitVecRes_INSERT_SUBVECTOR()
1317 Store = DAG.getStore(Store, dl, SubVec, SubVecPtr, in SplitVecRes_INSERT_SUBVECTOR()
2385 SDValue SubVec = N->getOperand(1); in SplitVecOp_INSERT_SUBVECTOR() local
2390 GetSplitVector(SubVec, Lo, Hi); in SplitVecOp_INSERT_SUBVECTOR()
4843 SDValue SubVec = N->getOperand(1); in WidenVecOp_INSERT_SUBVECTOR() local
4850 SubVec = GetWidenedVector(SubVec); in WidenVecOp_INSERT_SUBVECTOR()
4852 if (SubVec.getValueType() == InVec.getValueType() && InVec.isUndef() && in WidenVecOp_INSERT_SUBVECTOR()
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| H A D | SelectionDAGBuilder.cpp | 7116 SDValue SubVec = getValue(I.getOperand(1)); in visitIntrinsicCall() local
7127 setValue(&I, DAG.getNode(ISD::INSERT_SUBVECTOR, DL, ResultVT, Vec, SubVec, in visitIntrinsicCall()
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| H A D | DAGCombiner.cpp | 18236 SDValue SubVec = InsertVal.getOperand(0); in combineInsertEltToShuffle() local
18238 EVT SubVecVT = SubVec.getValueType(); in combineInsertEltToShuffle()
18271 ConcatOps[0] = SubVec; in combineInsertEltToShuffle()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCalls.cpp | 1852 Value *SubVec = II->getArgOperand(1); in visitCallInst() local
1856 auto *SubVecTy = dyn_cast<FixedVectorType>(SubVec->getType()); in visitCallInst()
1875 replaceInstUsesWith(CI, SubVec); in visitCallInst()
1890 Value *WidenShuffle = Builder.CreateShuffleVector(SubVec, WidenMask); in visitCallInst()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 6213 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec, in insert1BitVector()
6223 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec, in insert1BitVector()
6226 SubVec = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, SubVec, in insert1BitVector()
6233 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec, in insert1BitVector()
6272 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec, in insert1BitVector()
6274 SubVec = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, SubVec, in insert1BitVector()
6283 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec, in insert1BitVector()
6285 SubVec = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, SubVec, in insert1BitVector()
6304 SubVec = DAG.getNode(ISD::OR, dl, WideOpVT, SubVec, Vec); in insert1BitVector()
17571 SDValue SubVec = in lowerV4X128Shuffle() local
[all …]
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 3668 SDValue SubVec = Op.getOperand(1); in lowerINSERT_SUBVECTOR() local
3670 MVT SubVecVT = SubVec.getSimpleValueType(); in lowerINSERT_SUBVECTOR()
3697 SubVec = DAG.getBitcast(SubVecVT, SubVec); in lowerINSERT_SUBVECTOR()
3706 SubVec = DAG.getNode(ISD::ZERO_EXTEND, DL, ExtSubVecVT, SubVec); in lowerINSERT_SUBVECTOR()
3707 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, ExtVecVT, Vec, SubVec, in lowerINSERT_SUBVECTOR()
3727 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, ContainerVT, in lowerINSERT_SUBVECTOR()
3728 DAG.getUNDEF(ContainerVT), SubVec, in lowerINSERT_SUBVECTOR()
3738 SubVec, SlideupAmt, Mask, VL); in lowerINSERT_SUBVECTOR()
3797 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, InterSubVT, in lowerINSERT_SUBVECTOR()
3798 DAG.getUNDEF(InterSubVT), SubVec, in lowerINSERT_SUBVECTOR()
[all …]
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| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/IR/ |
| H A D | IRBuilder.h | 909 CallInst *CreateInsertVector(Type *DstType, Value *SrcVec, Value *SubVec,
912 {DstType, SubVec->getType()}, {SrcVec, SubVec, Idx},
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 8739 SDValue SubVec = DAG.getNode(ISD::UNDEF, dl, SubVT); in LowerEXTRACT_SUBVECTOR() local
8743 SubVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, SubVT, SubVec, Elt, in LowerEXTRACT_SUBVECTOR()
8749 return DAG.getNode(ARMISD::VCMPZ, dl, VT, SubVec, in LowerEXTRACT_SUBVECTOR()
15207 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, StoreType, in PerformTruncatingStoreCombine() local
15210 DAG.getStore(St->getChain(), DL, SubVec, BasePtr, St->getPointerInfo(), in PerformTruncatingStoreCombine()
19733 Value *SubVec = Builder.CreateExtractValue(VldN, Index); in lowerInterleavedLoad() local
19737 SubVec = Builder.CreateIntToPtr( in lowerInterleavedLoad()
19738 SubVec, in lowerInterleavedLoad()
19741 SubVecs[SV].push_back(SubVec); in lowerInterleavedLoad()
19750 auto &SubVec = SubVecs[SVI]; in lowerInterleavedLoad() local
[all …]
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 11404 Value *SubVec = Builder.CreateExtractValue(LdN, Index); in lowerInterleavedLoad() local
11408 SubVec = Builder.CreateIntToPtr( in lowerInterleavedLoad()
11409 SubVec, FixedVectorType::get(SVI->getType()->getElementType(), in lowerInterleavedLoad()
11411 SubVecs[SVI].push_back(SubVec); in lowerInterleavedLoad()
11420 auto &SubVec = SubVecs[SVI]; in lowerInterleavedLoad() local
11422 SubVec.size() > 1 ? concatenateVectors(Builder, SubVec) : SubVec[0]; in lowerInterleavedLoad()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Analysis/ |
| H A D | InstructionSimplify.cpp | 5738 Value *SubVec = Call->getArgOperand(1); in simplifyIntrinsic() local
5746 if (match(SubVec, m_Intrinsic<Intrinsic::experimental_vector_extract>( in simplifyIntrinsic()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 5540 SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, in lowerVECTOR_SHUFFLE() local
5543 Pieces.push_back(SubVec); in lowerVECTOR_SHUFFLE()
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