/netbsd/external/gpl2/texinfo/dist/doc/ |
H A D | pdfcolor.tex | 4 \def\cmykYellow{0 0 1 0} 8 \def\cmykPeach{0 0.50 0.70 0} 18 \def\cmykRed{0 1 1 0} 24 \def\cmykMagenta{0 1 0 0} 45 \def\cmykBlue{1 1 0 0} 47 \def\cmykCyan{1 0 0 0} 57 \def\cmykGreen{1 0 1 0} 69 \def\cmykBlack{0 0 0 1} 70 \def\cmykWhite{0 0 0 0} 148 \def\makefootline{ [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | ARMSchedule.td | 60 def WriteALU : SchedWrite; 61 def ReadALU : SchedRead; 70 def WriteCMP : SchedWrite; 79 def ReadMUL : SchedRead; 86 def ReadMAC : SchedRead; 89 def WriteDIV : SchedWrite; 92 def WriteLd : SchedWrite; 94 def WriteST : SchedWrite; 97 def WriteBr : SchedWrite; 98 def WriteBrL : SchedWrite; [all …]
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/netbsd/external/apache2/llvm/dist/clang/include/clang/Basic/ |
H A D | StmtNodes.td | 9 def Stmt : StmtNode<?, 1>; 10 def NullStmt : StmtNode<Stmt>; 11 def CompoundStmt : StmtNode<Stmt>; 12 def IfStmt : StmtNode<Stmt>; 13 def SwitchStmt : StmtNode<Stmt>; 14 def WhileStmt : StmtNode<Stmt>; 15 def DoStmt : StmtNode<Stmt>; 16 def ForStmt : StmtNode<Stmt>; 17 def GotoStmt : StmtNode<Stmt>; 20 def BreakStmt : StmtNode<Stmt>; [all …]
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H A D | DiagnosticGroups.td | 19 def ODR : DiagGroup<"odr">; 20 def : DiagGroup<"abi">; 108 def FloatConversion : 214 def DynamicExceptionSpec 285 def CXXPre2bCompatPedantic : 404 def : DiagGroup<"import">; 411 def IncompatiblePointerTypes 433 def : DiagGroup<"inline">; 504 def FunctionDefInObjCContainer : DiagGroup<"function-def-in-objc-container">; 573 def : DiagGroup<"synth">; [all …]
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H A D | DeclNodes.td | 12 def Decl : DeclNode<?, "", 1>; 14 def PragmaComment : DeclNode<Decl>; 40 def Binding : DeclNode<Value>; 43 def MSGuid : DeclNode<Value>; 74 def Using : DeclNode<Named>; 83 def ObjCImpl 93 def AccessSpec : DeclNode<Decl>; 94 def Friend : DeclNode<Decl>; 100 def Import : DeclNode<Decl>; 102 def OMPAllocate : DeclNode<Decl>; [all …]
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/netbsd/external/apache2/llvm/dist/llvm/include/llvm/IR/ |
H A D | IntrinsicsHexagonDep.td | 1070 def int_hexagon_A2_abs : 1079 def int_hexagon_A2_add : 1133 def int_hexagon_A2_and : 1166 def int_hexagon_A2_max : 1178 def int_hexagon_A2_min : 1190 def int_hexagon_A2_neg : 1199 def int_hexagon_A2_not : 1205 def int_hexagon_A2_or : 1211 def int_hexagon_A2_orp : 1217 def int_hexagon_A2_sat : [all …]
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H A D | IntrinsicsAArch64.td | 47 def int_aarch64_frint32z 50 def int_aarch64_frint64z 53 def int_aarch64_frint32x 56 def int_aarch64_frint64x 271 def int_aarch64_neon_pmull64 : 448 def int_aarch64_neon_vcvtfp2hf 496 def int_aarch64_neon_bfmmla 505 def int_aarch64_neon_bfcvt 507 def int_aarch64_neon_bfcvtn 509 def int_aarch64_neon_bfcvtn2 [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonIntrinsicsV5.td | 16 def: T_RP_pat<A2_addsp, int_hexagon_A2_addsp>; 17 def: T_PP_pat<A2_addpsat, int_hexagon_A2_addpsat>; 18 def: T_PP_pat<A2_minp, int_hexagon_A2_minp>; 19 def: T_PP_pat<A2_minup, int_hexagon_A2_minup>; 20 def: T_PP_pat<A2_maxp, int_hexagon_A2_maxp>; 21 def: T_PP_pat<A2_maxup, int_hexagon_A2_maxup>; 83 def: T_P_pat<S2_brevp, int_hexagon_S2_brevp>; 84 def: T_P_pat<S2_ct0p, int_hexagon_S2_ct0p>; 85 def: T_P_pat<S2_ct1p, int_hexagon_S2_ct1p>; 227 def: T_RR_pat<A4_orn, int_hexagon_A4_orn>; [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
H A D | RISCVSystemOperands.td | 77 def : SysReg<"uie", 0x004>; 78 def : SysReg<"utvec", 0x005>; 84 def : SysReg<"uepc", 0x041>; 87 def : SysReg<"utval", 0x043>; 88 def : SysReg<"uip", 0x044>; 177 def : SysReg<"sie", 0x104>; 185 def : SysReg<"sepc", 0x141>; 189 def : SysReg<"sip", 0x144>; 213 def : SysReg<"mie", 0x304>; 225 def : SysReg<"mip", 0x344>; [all …]
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H A D | RISCVSchedule.td | 24 def WriteNop : SchedWrite; 109 def ReadJmp : SchedRead; 110 def ReadJalr : SchedRead; 111 def ReadCSR : SchedRead; 112 def ReadMemBase : SchedRead; 113 def ReadFMemBase : SchedRead; 114 def ReadStoreData : SchedRead; 115 def ReadIALU : SchedRead; 199 def : WriteRes<WriteFLD16, []>; 200 def : WriteRes<WriteFMA16, []>; [all …]
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H A D | RISCVSchedRocket.td | 14 def RocketModel : SchedMachineModel { 170 def : WriteRes<WriteCSR, []>; 171 def : WriteRes<WriteNop, []>; 177 def : ReadAdvance<ReadJmp, 0>; 178 def : ReadAdvance<ReadJalr, 0>; 179 def : ReadAdvance<ReadCSR, 0>; 182 def : ReadAdvance<ReadIALU, 0>; 188 def : ReadAdvance<ReadIDiv, 0>; 190 def : ReadAdvance<ReadIMul, 0>; 204 def : ReadAdvance<ReadFMA32, 0>; [all …]
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H A D | RISCVSchedSiFive7.td | 12 def SiFive7Model : SchedMachineModel { 159 def : WriteRes<WriteNop, []>; 165 def : ReadAdvance<ReadJmp, 0>; 166 def : ReadAdvance<ReadJalr, 0>; 167 def : ReadAdvance<ReadCSR, 0>; 170 def : ReadAdvance<ReadIALU, 0>; 171 def : ReadAdvance<ReadIALU32, 0>; 176 def : ReadAdvance<ReadIDiv, 0>; 178 def : ReadAdvance<ReadIMul, 0>; 192 def : ReadAdvance<ReadFMA32, 0>; [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
H A D | PPCSchedule.td | 12 def IIC_IntSimple : InstrItinClass; 13 def IIC_IntGeneral : InstrItinClass; 14 def IIC_IntCompare : InstrItinClass; 15 def IIC_IntISEL : InstrItinClass; 16 def IIC_IntDivD : InstrItinClass; 17 def IIC_IntDivW : InstrItinClass; 18 def IIC_IntMFFS : InstrItinClass; 19 def IIC_IntMFVSCR : InstrItinClass; 20 def IIC_IntMTFSB0 : InstrItinClass; 21 def IIC_IntMTSRD : InstrItinClass; [all …]
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/netbsd/external/apache2/llvm/dist/clang/include/clang/AST/ |
H A D | CommentHTMLNamedCharacterReferences.td | 15 def : NCR<"copy", 0x000A9>; 16 def : NCR<"COPY", 0x000A9>; 17 def : NCR<"trade", 0x02122>; 18 def : NCR<"TRADE", 0x02122>; 19 def : NCR<"reg", 0x000AE>; 20 def : NCR<"REG", 0x000AE>; 21 def : NCR<"lt", 0x0003C>; 22 def : NCR<"Lt", 0x0003C>; 23 def : NCR<"LT", 0x0003C>; 24 def : NCR<"gt", 0x0003E>; [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUSearchableTables.td | 19 def RsrcIntrinsics : GenericTable { 50 def Gfx9BufferFormat : GcnBufferFormatTable { 59 def getGfx9BufferFormatInfo : SearchIndex { 63 def getGfx10PlusBufferFormatInfo : SearchIndex { 178 def SourcesOfDivergence : GenericTable { 208 def : SourceOfDivergence<int_amdgcn_ds_fadd>; 209 def : SourceOfDivergence<int_amdgcn_ds_fmin>; 300 def : SourceOfDivergence<int_amdgcn_if>; 301 def : SourceOfDivergence<int_amdgcn_else>; 302 def : SourceOfDivergence<int_amdgcn_loop>; [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
H A D | AVRDevices.td | 162 def FamilyAVR2 : Family<"avr2", 166 def FamilyAVR25 : Family<"avr25", 170 def FamilyAVR3 : Family<"avr3", 173 def FamilyAVR31 : Family<"avr31", 176 def FamilyAVR35 : Family<"avr35", 180 def FamilyAVR4 : Family<"avr4", 185 def FamilyAVR5 : Family<"avr5", 190 def FamilyAVR51 : Family<"avr51", 193 def FamilyAVR6 : Family<"avr6", 200 def FamilyXMEGA : Family<"xmega", [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
H A D | MipsSchedule.td | 12 def ALU : FuncUnit; 13 def IMULDIV : FuncUnit; 19 def IIM16Alu : InstrItinClass; 20 def IIPseudo : InstrItinClass; 22 def II_ABS : InstrItinClass; 23 def II_ADDI : InstrItinClass; 24 def II_ADDIU : InstrItinClass; 25 def II_ADDIUPC : InstrItinClass; 26 def II_ADD : InstrItinClass; 27 def II_ADDU : InstrItinClass; [all …]
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H A D | MipsScheduleGeneric.td | 16 def MipsGenericModel : SchedMachineModel { 974 def : InstRW<[GenericWriteFPUCmp], 976 def : InstRW<[GenericWriteFPUCmp], 979 def : InstRW<[GenericWriteFPUL], 982 def : InstRW<[GenericWriteFPUL], 985 def : InstRW<[GenericWriteFPUL], 988 def : InstRW<[GenericWriteFPUL], 991 def : InstRW<[GenericWriteFPUL], 994 def : InstRW<[GenericWriteFPUS], 1157 def : InstRW<[GenericDSPShort], [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
H A D | SparcRegisterInfo.td | 215 def C0 : Ri< 0, "C0">; 216 def C1 : Ri< 1, "C1">; 217 def C2 : Ri< 2, "C2">; 218 def C3 : Ri< 3, "C3">; 219 def C4 : Ri< 4, "C4">; 220 def C5 : Ri< 5, "C5">; 221 def C6 : Ri< 6, "C6">; 222 def C7 : Ri< 7, "C7">; 223 def C8 : Ri< 8, "C8">; 224 def C9 : Ri< 9, "C9">; [all …]
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/netbsd/external/gpl3/gdb/dist/include/opcode/ |
H A D | visium.h | 43 #define def (MASK_DEF | MASK_GR5 | MASK_GR6) macro 234 { "adc.b", mode_dab, class3|(1<<21)|(1), def }, 235 { "adc.l", mode_dab, class3|(1<<21)|(4), def }, 240 { "addi", mode_ai, class2, def }, 255 { "brr", mode_ci, class0, def }, 298 { "movil", mode_ai, class2|(4<<21), def }, 299 { "moviq", mode_ai, class2|(6<<21), def }, 300 { "moviu", mode_ai, class2|(5<<21), def }, 303 { "nop", mode_s, class0, def }, 325 { "subi", mode_ai, class2|(2<<21), def }, [all …]
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/netbsd/external/gpl3/binutils.old/dist/include/opcode/ |
H A D | visium.h | 43 #define def (MASK_DEF | MASK_GR5 | MASK_GR6) macro 234 { "adc.b", mode_dab, class3|(1<<21)|(1), def }, 235 { "adc.l", mode_dab, class3|(1<<21)|(4), def }, 240 { "addi", mode_ai, class2, def }, 255 { "brr", mode_ci, class0, def }, 298 { "movil", mode_ai, class2|(4<<21), def }, 299 { "moviq", mode_ai, class2|(6<<21), def }, 300 { "moviu", mode_ai, class2|(5<<21), def }, 303 { "nop", mode_s, class0, def }, 325 { "subi", mode_ai, class2|(2<<21), def }, [all …]
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/netbsd/external/gpl3/binutils/dist/include/opcode/ |
H A D | visium.h | 43 #define def (MASK_DEF | MASK_GR5 | MASK_GR6) macro 234 { "adc.b", mode_dab, class3|(1<<21)|(1), def }, 235 { "adc.l", mode_dab, class3|(1<<21)|(4), def }, 240 { "addi", mode_ai, class2, def }, 255 { "brr", mode_ci, class0, def }, 298 { "movil", mode_ai, class2|(4<<21), def }, 299 { "moviq", mode_ai, class2|(6<<21), def }, 300 { "moviu", mode_ai, class2|(5<<21), def }, 303 { "nop", mode_s, class0, def }, 325 { "subi", mode_ai, class2|(2<<21), def }, [all …]
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/netbsd/external/gpl3/gdb.old/dist/include/opcode/ |
H A D | visium.h | 43 #define def (MASK_DEF | MASK_GR5 | MASK_GR6) macro 234 { "adc.b", mode_dab, class3|(1<<21)|(1), def }, 235 { "adc.l", mode_dab, class3|(1<<21)|(4), def }, 240 { "addi", mode_ai, class2, def }, 255 { "brr", mode_ci, class0, def }, 298 { "movil", mode_ai, class2|(4<<21), def }, 299 { "moviq", mode_ai, class2|(6<<21), def }, 300 { "moviu", mode_ai, class2|(5<<21), def }, 303 { "nop", mode_s, class0, def }, 325 { "subi", mode_ai, class2|(2<<21), def }, [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
H A D | AArch64SchedExynosM4.td | 626 def : InstRW<[WriteST, 679 def : InstRW<[WriteVLD, 684 def : InstRW<[WriteVLD, 688 def : InstRW<[WriteVLD, 707 def : InstRW<[WriteVST, 714 def : InstRW<[WriteVST, 720 def : InstRW<[WriteVST, 835 def : InstRW<[WriteVLD, 838 def : InstRW<[WriteVLD, 867 def : InstRW<[WriteVLD, [all …]
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H A D | AArch64SchedExynosM3.td | 514 def : InstRW<[M3WriteLD, 517 def : InstRW<[M3WriteLB, 529 def : InstRW<[WriteST, 564 def : InstRW<[WriteVLD, 569 def : InstRW<[WriteVLD, 573 def : InstRW<[WriteVLD, 586 def : InstRW<[WriteVST, 593 def : InstRW<[WriteVST, 598 def : InstRW<[WriteVST, 790 def : InstRW<[WriteVST, [all …]
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