| /netbsd/sys/external/bsd/drm2/dist/drm/vmwgfx/ |
| H A D | vmwgfx_drv.c | 451 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); in vmw_request_device()
457 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); in vmw_request_device()
484 vmw_fifo_release(dev_priv, &dev_priv->fifo); in vmw_request_device()
529 vmw_fifo_release(dev_priv, &dev_priv->fifo); in vmw_release_device_late()
642 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); in vmw_driver_load()
722 dev_priv->memory_size -= dev_priv->vram_size; in vmw_driver_load()
757 dev_priv->texture_max_width = vmw_read(dev_priv, in vmw_driver_load()
761 dev_priv->texture_max_height = vmw_read(dev_priv, in vmw_driver_load()
766 dev_priv->prim_bb_mem = dev_priv->vram_size; in vmw_driver_load()
878 dev_priv->fman = vmw_fence_manager_init(dev_priv); in vmw_driver_load()
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| H A D | vmwgfx_irq.c | 107 status = bus_space_read_4(dev_priv->iot, dev_priv->ioh, in vmw_irq_handler()
116 bus_space_write_4(dev_priv->iot, dev_priv->ioh, in vmw_irq_handler()
235 if (dev_priv->cman) { in vmw_fallback_wait()
315 DRM_SPIN_WAKEUP_ALL(&dev_priv->fence_queue, &dev_priv->fence_lock); in vmw_fallback_wait()
333 bus_space_write_4(dev_priv->iot, dev_priv->ioh, in vmw_generic_waiter_add()
339 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); in vmw_generic_waiter_add()
350 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); in vmw_generic_waiter_remove()
440 status = bus_space_read_4(dev_priv->iot, dev_priv->ioh, in vmw_irq_preinstall()
442 bus_space_write_4(dev_priv->iot, dev_priv->ioh, VMWGFX_IRQSTATUS_PORT, in vmw_irq_preinstall()
464 status = bus_space_read_4(dev_priv->iot, dev_priv->ioh, in vmw_irq_uninstall()
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| H A D | vmwgfx_fifo.c | 58 if (!dev_priv->has_mob) in vmw_fifo_have_3d()
133 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); in vmw_fifo_init()
134 dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE); in vmw_fifo_init()
135 dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES); in vmw_fifo_init()
168 atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno); in vmw_fifo_init()
282 DRM_SPIN_WAKEUP_ALL(&dev_priv->fifo_queue, &dev_priv->fifo_lock); in vmw_fifo_wait_noirq()
439 if (dev_priv->cman) in vmw_fifo_reserve_dx()
547 if (dev_priv->cman) in vmw_fifo_commit()
562 if (dev_priv->cman) in vmw_fifo_commit_flush()
579 if (dev_priv->cman) in vmw_fifo_flush()
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| /netbsd/sys/external/bsd/drm/dist/shared-core/ |
| H A D | radeon_cp.c | 808 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start); in radeon_set_igpgart()
880 (dev_priv->gart_vm_start + dev_priv->gart_size - 1)); in rs600_set_igpgart()
887 (dev_priv->gart_vm_start + dev_priv->gart_size - 1)); in rs600_set_igpgart()
1228 base = dev_priv->fb_location + dev_priv->fb_size; in radeon_do_init_cp()
1240 dev_priv->gart_vm_start = dev_priv->fb_location + in radeon_do_init_cp()
1261 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle; in radeon_do_init_cp()
1262 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle in radeon_do_init_cp()
1288 dev_priv->pcigart_offset + dev_priv->fb_location; in radeon_do_init_cp()
1290 dev_priv->pcigart_offset + dev_priv->fb_aper_offset; in radeon_do_init_cp()
1958 dev_priv->ring.tail &= dev_priv->ring.tail_mask; in radeon_commit_ring()
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| H A D | savage_bci.c | 215 dev_priv->head.next = &dev_priv->tail; in savage_freelist_init()
220 dev_priv->tail.prev = &dev_priv->head; in savage_freelist_init()
299 dev_priv->nr_dma_pages = dev_priv->cmd_dma->size / in savage_dma_init()
340 if (dev_priv->cmd_dma == &dev_priv->fake_dma) in savage_dma_wait()
355 if (dev_priv->wait_evnt(dev_priv, in savage_dma_wait()
384 dev_priv->dma_flush(dev_priv); in savage_dma_alloc()
388 dev_priv->dma_pages[i].age = dev_priv->last_dma_age; in savage_dma_alloc()
413 savage_dma_wait(dev_priv, dev_priv->current_dma_page); in savage_dma_alloc()
815 dev_priv->cmd_dma = &dev_priv->fake_dma; in savage_do_init_bci()
906 if (dev_priv->cmd_dma == &dev_priv->fake_dma) { in savage_do_cleanup_bci()
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| H A D | i915_suspend.c | 148 dev_priv->saveCR[i] = in i915_save_vga()
164 dev_priv->saveGR[i] = in i915_save_vga()
167 dev_priv->saveGR[0x10] = in i915_save_vga()
169 dev_priv->saveGR[0x11] = in i915_save_vga()
171 dev_priv->saveGR[0x18] = in i915_save_vga()
176 dev_priv->saveSR[i] = in i915_save_vga()
201 dev_priv->saveSR[i]); in i915_restore_vga()
212 dev_priv->saveGR[i]); in i915_restore_vga()
215 dev_priv->saveGR[0x10]); in i915_restore_vga()
217 dev_priv->saveGR[0x11]); in i915_restore_vga()
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| H A D | r600_cp.c | 1806 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0; in r600_cp_init_ring_buffer()
1813 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0; in r600_cp_init_ring_buffer()
2052 base = dev_priv->fb_location + dev_priv->fb_size; in r600_do_init_cp()
2085 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle; in r600_do_init_cp()
2086 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle in r600_do_init_cp()
2118 dev_priv->pcigart_offset + dev_priv->fb_location; in r600_do_init_cp()
2120 dev_priv->pcigart_offset + dev_priv->fb_aper_offset; in r600_do_init_cp()
2323 src = dev_priv->back_offset + dev_priv->fb_location; in r600_cp_dispatch_swap()
2324 dst = dev_priv->front_offset + dev_priv->fb_location; in r600_cp_dispatch_swap()
2328 src = dev_priv->front_offset + dev_priv->fb_location; in r600_cp_dispatch_swap()
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| H A D | r128_cce.c | 214 if (GET_RING_HEAD(dev_priv) == dev_priv->ring.tail) { in r128_do_cce_idle()
240 dev_priv->cce_mode | dev_priv->ring.size_l2qw in r128_do_cce_start()
449 dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch / 8) << 21) | in r128_do_init_cce()
451 dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch / 8) << 21) | in r128_do_init_cce()
456 dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) | in r128_do_init_cce()
528 dev_priv->cce_ring->handle = (void *)dev_priv->cce_ring->offset; in r128_do_init_cce()
542 dev_priv->ring.start = (u32 *) dev_priv->cce_ring->handle; in r128_do_init_cce()
543 dev_priv->ring.end = ((u32 *) dev_priv->cce_ring->handle in r128_do_init_cce()
548 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; in r128_do_init_cce()
652 if (dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4) { in r128_cce_start()
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| H A D | mga_dma.c | 308 dev_priv->head = dev_priv->tail = NULL; in mga_freelist_cleanup()
402 if (!dev_priv) in mga_driver_load()
588 dev_priv->warp->handle, dev_priv->primary->handle, in mga_do_agp_dma_bootstrap()
720 err = drm_addmap(dev, dev_priv->mmio_base, dev_priv->mmio_size, in mga_do_dma_bootstrap()
902 dev_priv->prim.status = (u32 *) dev_priv->status->handle; in mga_do_init_dma()
910 dev_priv->prim.start = (u8 *) dev_priv->primary->handle; in mga_do_init_dma()
911 dev_priv->prim.end = ((u8 *) dev_priv->primary->handle in mga_do_init_dma()
913 dev_priv->prim.size = dev_priv->primary->size; in mga_do_init_dma()
916 dev_priv->prim.space = dev_priv->prim.size; in mga_do_init_dma()
924 dev_priv->prim.status[0] = dev_priv->primary->offset; in mga_do_init_dma()
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| H A D | i915_irq.c | 220 if (dev_priv->sarea_priv) in i915_driver_irq_handler()
256 dev_priv->counter++; in i915_emit_irq()
258 dev_priv->counter = 1; in i915_emit_irq()
259 if (dev_priv->sarea_priv) in i915_emit_irq()
260 dev_priv->sarea_priv->last_enqueue = dev_priv->counter; in i915_emit_irq()
324 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); in i915_wait_irq()
345 if (!dev_priv) { in i915_irq_emit()
368 if (!dev_priv) { in i915_irq_wait()
421 if (!dev_priv) { in i915_vblank_pipe_set()
435 if (!dev_priv) { in i915_vblank_pipe_get()
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| /netbsd/sys/external/bsd/drm2/dist/drm/savage/ |
| H A D | savage_bci.c | 229 dev_priv->head.next = &dev_priv->tail; in savage_freelist_init()
234 dev_priv->tail.prev = &dev_priv->head; in savage_freelist_init()
313 dev_priv->nr_dma_pages = dev_priv->cmd_dma->size / in savage_dma_init()
355 if (dev_priv->cmd_dma == &dev_priv->fake_dma) in savage_dma_wait()
370 if (dev_priv->wait_evnt(dev_priv, in savage_dma_wait()
399 dev_priv->dma_flush(dev_priv); in savage_dma_alloc()
403 dev_priv->dma_pages[i].age = dev_priv->last_dma_age; in savage_dma_alloc()
428 savage_dma_wait(dev_priv, dev_priv->current_dma_page); in savage_dma_alloc()
815 dev_priv->cmd_dma = &dev_priv->fake_dma; in savage_do_init_bci()
906 if (dev_priv->cmd_dma == &dev_priv->fake_dma) { in savage_do_cleanup_bci()
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| /netbsd/sys/external/bsd/drm2/dist/drm/via/ |
| H A D | via_dma.c | 100 (dev_priv->dma_high + hw_addr - dev_priv->dma_low) : in via_cmdbuf_space()
115 (dev_priv->dma_wrap + dev_priv->dma_low - hw_addr)); in via_cmdbuf_lag()
164 return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low); in via_check_dma()
189 if (!dev_priv || !dev_priv->mmio) { in via_initialize()
224 dev_priv->ring.virtual_start = dev_priv->ring.map.handle; in via_initialize()
226 dev_priv->dma_ptr = dev_priv->ring.virtual_start; in via_initialize()
404 return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low); in via_get_dma()
431 dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4; in via_hook_segment()
433 dev_priv->last_pause_ptr = via_get_dma(dev_priv) - 1; in via_hook_segment()
569 dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4; in via_cmdbuf_start()
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| H A D | via_irq.c | 124 dev_priv->nsec_per_vblank = in via_driver_irq_handler()
126 dev_priv->last_vblank) >> 4; in via_driver_irq_handler()
174 if (dev_priv) { in viadrv_acknowledge_irqs()
178 dev_priv->irq_pending_mask); in viadrv_acknowledge_irqs()
229 if (!dev_priv) { in via_driver_irq_wait()
247 masks = dev_priv->irq_masks; in via_driver_irq_wait()
295 if (dev_priv) { in via_driver_irq_preinstall()
296 cur_irq = dev_priv->via_irqs; in via_driver_irq_preinstall()
351 if (!dev_priv) in via_driver_irq_postinstall()
356 | dev_priv->irq_enable_mask); in via_driver_irq_postinstall()
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| /netbsd/sys/external/bsd/drm2/dist/drm/i915/ |
| H A D | intel_pch.c | 25 WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv)); in intel_pch_type()
29 WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv)); in intel_pch_type()
34 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); in intel_pch_type()
35 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)); in intel_pch_type()
39 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); in intel_pch_type()
40 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv)); in intel_pch_type()
44 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); in intel_pch_type()
45 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)); in intel_pch_type()
51 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv)); in intel_pch_type()
56 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv)); in intel_pch_type()
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| H A D | i915_irq.c | 510 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); in i915_has_asle()
782 IS_G4X(dev_priv) || IS_GEN(dev_priv, 2) || in i915_get_crtc_scanoutpos()
1275 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) in i9xx_pipe_crc_irq_handler()
1460 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in i9xx_hpd_irq_ack()
1497 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || in i9xx_hpd_irq_handler()
2353 if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) && in gen8_de_irq_handler()
2687 if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv)) in ibx_irq_reset()
3228 else if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv)) in ibx_irq_postinstall()
3236 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) || in ibx_irq_postinstall()
3922 if (HAS_GT_UC(dev_priv) && INTEL_GEN(dev_priv) < 11) in intel_irq_init()
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| H A D | i915_drv.h | 1415 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info) argument
1417 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) argument
1529 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) argument
1656 #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv)) argument
1657 #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv)) argument
1682 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \ argument
1683 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
1712 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv)) argument
1715 (IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9))
1739 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7) argument
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| H A D | i915_drv.c | 235 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_setup_mchbar()
240 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { in intel_setup_mchbar()
258 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { in intel_setup_mchbar()
273 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { in intel_teardown_mchbar()
523 intel_uncore_init_early(&dev_priv->uncore, dev_priv); in i915_driver_early_probe()
551 intel_gt_init_early(&dev_priv->gt, dev_priv); in i915_driver_early_probe()
587 intel_uncore_fini_early(&dev_priv->uncore, dev_priv); in i915_driver_early_probe()
616 intel_uncore_fini_early(&dev_priv->uncore, dev_priv); in i915_driver_late_release()
1109 if (INTEL_GEN(dev_priv) < 9 || !HAS_DISPLAY(dev_priv)) in intel_get_dram_info()
1267 if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) { in i915_driver_hw_probe()
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| H A D | i915_suspend.c | 45 if (INTEL_GEN(dev_priv) <= 4) in i915_save_display()
49 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv)) in i915_save_display()
56 if (INTEL_GEN(dev_priv) <= 4) in i915_restore_display()
63 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv)) in i915_restore_display()
74 i915_save_display(dev_priv); in i915_save_state()
76 if (IS_GEN(dev_priv, 4)) in i915_save_state()
81 if (INTEL_GEN(dev_priv) < 7) in i915_save_state()
88 if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) { in i915_save_state()
115 if (IS_GEN(dev_priv, 4)) in i915_restore_state()
121 if (INTEL_GEN(dev_priv) < 7) in i915_restore_state()
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| /netbsd/sys/external/bsd/drm2/dist/drm/i915/display/ |
| H A D | intel_psr.c | 512 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) in hsw_activate_psr2()
746 if (transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder)) in intel_psr_activate()
772 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) in intel_psr_enable_source()
775 if (dev_priv->psr.psr2_enabled && (IS_GEN(dev_priv, 9) && in intel_psr_enable_source()
888 if (transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder)) { in intel_psr_exit()
1236 if (dev_priv->psr.busy_frontbuffer_bits || dev_priv->psr.active) in intel_psr_work()
1298 if (!dev_priv->psr.psr2_enabled || !dev_priv->psr.active) in tgl_dc3co_flush()
1385 if (INTEL_GEN(dev_priv) < 9 || !dev_priv->vbt.psr.enable) in intel_psr_init()
1389 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) in intel_psr_init()
1394 dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link; in intel_psr_init()
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| H A D | intel_cdclk.c | 504 if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) { in vlv_program_pfi_credits()
1788 if (INTEL_GEN(dev_priv) < 10 && !IS_GEN9_LP(dev_priv)) in intel_cdclk_needs_cd2x_update()
1918 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) in intel_pixel_rate_to_cdclk()
2428 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) in intel_compute_max_dotclk()
2507 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk; in intel_update_max_cdclk()
2527 dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw); in intel_update_cdclk()
2617 dev_priv->rawclk_freq = cnp_rawclk(dev_priv); in intel_update_rawclk()
2619 dev_priv->rawclk_freq = pch_rawclk(dev_priv); in intel_update_rawclk()
2621 dev_priv->rawclk_freq = vlv_hrawclk(dev_priv); in intel_update_rawclk()
2622 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) in intel_update_rawclk()
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| H A D | intel_fbc.c | 291 if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) { in gen7_fbc_activate()
438 if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv)) in find_compression_threshold()
572 if (IS_GEN(dev_priv, 2) || IS_GEN(dev_priv, 3)) in stride_is_valid()
623 } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { in intel_fbc_hw_tracking_covers_screen()
653 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) in intel_fbc_update_state_cache()
737 if (INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) && in intel_fbc_can_activate()
760 if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) && in intel_fbc_can_activate()
1155 if ((IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) && in intel_fbc_enable()
1309 if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) in intel_sanitize_fbc_option()
1319 (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))) { in need_fbc_vtd_wa()
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| H A D | intel_fifo_underrun.c | 67 for_each_pipe(dev_priv, pipe) { in ivb_can_enable_err_int()
85 for_each_pipe(dev_priv, pipe) { in cpt_can_enable_serr_int()
269 if (HAS_GMCH(dev_priv)) in __intel_set_cpu_fifo_underrun_reporting()
273 else if (IS_GEN(dev_priv, 7)) in __intel_set_cpu_fifo_underrun_reporting()
275 else if (INTEL_GEN(dev_priv) >= 8) in __intel_set_cpu_fifo_underrun_reporting()
348 if (HAS_PCH_IBX(dev_priv)) in intel_set_pch_fifo_underrun_reporting()
380 if (HAS_GMCH(dev_priv) && in intel_cpu_fifo_underrun_irq_handler()
426 spin_lock_irq(&dev_priv->irq_lock); in intel_check_cpu_fifo_underruns()
432 if (HAS_GMCH(dev_priv)) in intel_check_cpu_fifo_underruns()
434 else if (IS_GEN(dev_priv, 7)) in intel_check_cpu_fifo_underruns()
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| H A D | intel_hotplug.c | 109 if (IS_CNL_WITH_PORT_F(dev_priv)) in intel_hpd_pin_default()
274 if (dev_priv->display_irqs_enabled && dev_priv->display.hpd_irq_setup) in intel_hpd_irq_storm_reenable_work()
275 dev_priv->display.hpd_irq_setup(dev_priv); in intel_hpd_irq_storm_reenable_work()
383 dev_priv->hotplug.event_bits = 0; in i915_hotplug_work_func()
385 dev_priv->hotplug.retry_bits = 0; in i915_hotplug_work_func()
467 spin_lock(&dev_priv->irq_lock); in intel_hpd_irq_handler()
517 WARN_ONCE(!HAS_GMCH(dev_priv), in intel_hpd_irq_handler()
550 dev_priv->display.hpd_irq_setup(dev_priv); in intel_hpd_irq_handler()
560 queue_work(dev_priv->hotplug.dp_wq, &dev_priv->hotplug.dig_port_work); in intel_hpd_irq_handler()
595 if (dev_priv->display_irqs_enabled && dev_priv->display.hpd_irq_setup) { in intel_hpd_init()
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| /netbsd/sys/external/bsd/drm2/dist/drm/r128/ |
| H A D | r128_cce.c | 218 if (GET_RING_HEAD(dev_priv) == dev_priv->ring.tail) { in r128_do_cce_idle()
244 dev_priv->cce_mode | dev_priv->ring.size_l2qw in r128_do_cce_start()
367 if (dev_priv == NULL) in r128_do_init_cce()
457 dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch / 8) << 21) | in r128_do_init_cce()
459 dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch / 8) << 21) | in r128_do_init_cce()
461 dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) | in r128_do_init_cce()
464 dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) | in r128_do_init_cce()
551 dev_priv->ring.start = (u32 *) dev_priv->cce_ring->handle; in r128_do_init_cce()
552 dev_priv->ring.end = ((u32 *) dev_priv->cce_ring->handle in r128_do_init_cce()
557 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; in r128_do_init_cce()
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| /netbsd/sys/external/bsd/drm2/dist/drm/mga/ |
| H A D | mga_dma.c | 306 dev_priv->head = dev_priv->tail = NULL; in mga_freelist_cleanup()
419 if (!dev_priv) in mga_driver_load()
599 dev_priv->warp->handle, dev_priv->primary->handle, in mga_do_agp_dma_bootstrap()
734 err = drm_legacy_addmap(dev, dev_priv->mmio_base, dev_priv->mmio_size, in mga_do_dma_bootstrap()
905 dev_priv->prim.status = (u32 *) dev_priv->status->handle; in mga_do_init_dma()
917 dev_priv->prim.start = (u8 *) dev_priv->primary->handle; in mga_do_init_dma()
918 dev_priv->prim.end = ((u8 *) dev_priv->primary->handle in mga_do_init_dma()
920 dev_priv->prim.size = dev_priv->primary->size; in mga_do_init_dma()
923 dev_priv->prim.space = dev_priv->prim.size; in mga_do_init_dma()
931 dev_priv->prim.status[0] = dev_priv->primary->offset; in mga_do_init_dma()
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