/netbsd/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
H A D | amdgpu_hwmgr.c | 111 hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK | in hwmgr_early_init() 122 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init() 127 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init() 132 hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK | in hwmgr_early_init() 140 hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK; in hwmgr_early_init() 153 hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK); in hwmgr_early_init() 158 hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK); in hwmgr_early_init() 169 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init() 179 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init() 452 if (hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK) in hwmgr_set_user_specify_caps() [all …]
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H A D | amdgpu_vega10_hwmgr.c | 146 hwmgr->feature_mask & PP_ULV_MASK ? true : false; in vega10_set_default_registry_data() 158 hwmgr->feature_mask & PP_AVFS_MASK ? true : false; in vega10_set_default_registry_data() 2843 uint32_t i, feature_mask = 0; in vega10_stop_dpm() local 2859 feature_mask |= data->smu_features[i]. in vega10_stop_dpm() 2882 uint32_t i, feature_mask = 0; in vega10_start_dpm() local 2888 feature_mask |= data->smu_features[i]. in vega10_start_dpm() 2897 true, feature_mask)) { in vega10_start_dpm() 2900 feature_mask) in vega10_start_dpm() 5343 uint32_t feature_mask = 0; in vega10_disable_power_features_for_compute_performance() local 5369 if (feature_mask) in vega10_disable_power_features_for_compute_performance() [all …]
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H A D | amdgpu_vega20_hwmgr.c | 107 if (!(hwmgr->feature_mask & PP_PCIE_DPM_MASK)) in vega20_set_default_registry_data() 110 if (!(hwmgr->feature_mask & PP_SCLK_DPM_MASK)) in vega20_set_default_registry_data() 113 if (!(hwmgr->feature_mask & PP_SOCCLK_DPM_MASK)) in vega20_set_default_registry_data() 116 if (!(hwmgr->feature_mask & PP_MCLK_DPM_MASK)) in vega20_set_default_registry_data() 122 if (!(hwmgr->feature_mask & PP_ULV_MASK)) in vega20_set_default_registry_data() 1821 (feature_mask & FEATURE_DPM_UCLK_MASK)) { in vega20_upload_dpm_min_level() 1831 (feature_mask & FEATURE_DPM_UVD_MASK)) { in vega20_upload_dpm_min_level() 1850 (feature_mask & FEATURE_DPM_VCE_MASK)) { in vega20_upload_dpm_min_level() 1872 (feature_mask & FEATURE_DPM_FCLK_MASK)) { in vega20_upload_dpm_min_level() 1926 (feature_mask & FEATURE_DPM_UVD_MASK)) { in vega20_upload_dpm_max_level() [all …]
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H A D | amdgpu_smu7_clockpowergating.c | 175 if (!(hwmgr->feature_mask & PP_ENABLE_GFX_CG_THRU_SMU)) in smu7_update_clock_gatings()
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H A D | amdgpu_smu7_hwmgr.c | 195 if (hwmgr->feature_mask & PP_SMC_VOLTAGE_CONTROL_MASK) in smu7_enable_smc_voltage_controller() 1106 if (!(hwmgr->feature_mask & PP_UVD_HANDSHAKE_MASK)) in smu7_enable_sclk_mclk_dpm() 1578 data->mclk_dpm_key_disabled = hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true; in smu7_init_dpm_defaults() 1579 data->sclk_dpm_key_disabled = hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true; in smu7_init_dpm_defaults() 1580 data->pcie_dpm_key_disabled = hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true; in smu7_init_dpm_defaults() 1588 data->ulv_supported = hwmgr->feature_mask & PP_ULV_MASK ? true : false; in smu7_init_dpm_defaults() 1672 if ((hwmgr->pp_table_version != PP_TABLE_V0) && (hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK) in smu7_init_dpm_defaults() 2233 if (hwmgr->feature_mask & PP_OD_FUZZY_FAN_CONTROL_MASK) in smu7_thermal_parameter_init() 3953 if (hwmgr->feature_mask & PP_VBI_TIME_SUPPORT_MASK) { in smu7_notify_smc_display()
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/netbsd/sys/external/bsd/drm2/dist/drm/amd/powerplay/ |
H A D | amdgpu_navi10_ppt.c | 336 uint32_t *feature_mask, uint32_t num) in navi10_get_allowed_feature_mask() argument 343 memset(feature_mask, 0, sizeof(uint32_t) * num); in navi10_get_allowed_feature_mask() 380 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) in navi10_get_allowed_feature_mask() 391 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); in navi10_get_allowed_feature_mask() 400 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT); in navi10_get_allowed_feature_mask() 410 *(uint64_t *)feature_mask &= in navi10_get_allowed_feature_mask() 414 *(uint64_t *)feature_mask &= in navi10_get_allowed_feature_mask() 1197 uint32_t feature_mask[2]; in navi10_is_dpm_running() local 1199 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2); in navi10_is_dpm_running() 1200 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] | in navi10_is_dpm_running() [all …]
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H A D | amdgpu_smu_v12_0.c | 331 uint32_t *feature_mask, uint32_t num) in smu_v12_0_get_enabled_mask() argument 336 if (!feature_mask || num < 2) in smu_v12_0_get_enabled_mask() 353 feature_mask[0] = feature_mask_low; in smu_v12_0_get_enabled_mask() 354 feature_mask[1] = feature_mask_high; in smu_v12_0_get_enabled_mask()
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H A D | amdgpu_smu_v11_0.c | 838 uint32_t feature_mask[2]; in smu_v11_0_set_allowed_mask() local 847 feature_mask[1]); in smu_v11_0_set_allowed_mask() 852 feature_mask[0]); in smu_v11_0_set_allowed_mask() 862 uint32_t *feature_mask, uint32_t num) in smu_v11_0_get_enabled_mask() argument 868 if (!feature_mask || num < 2) in smu_v11_0_get_enabled_mask() 886 feature_mask[0] = feature_mask_low; in smu_v11_0_get_enabled_mask() 887 feature_mask[1] = feature_mask_high; in smu_v11_0_get_enabled_mask() 889 bitmap_copy((unsigned long *)feature_mask, feature->enabled, in smu_v11_0_get_enabled_mask() 900 uint32_t feature_mask[2]; in smu_v11_0_system_features_control() local 912 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2); in smu_v11_0_system_features_control() [all …]
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H A D | amdgpu_smu.c | 77 uint32_t feature_mask[2] = { 0 }; in smu_sys_get_pp_feature_mask() local 85 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2); in smu_sys_get_pp_feature_mask() 90 feature_mask[1], feature_mask[0]); in smu_sys_get_pp_feature_mask() 116 uint64_t feature_mask, in smu_feature_update_enable_state() argument 126 feature_low = (feature_mask >> 0 ) & 0xffffffff; in smu_feature_update_enable_state() 127 feature_high = (feature_mask >> 32) & 0xffffffff; in smu_feature_update_enable_state() 152 (unsigned long *)(&feature_mask), SMU_FEATURE_MAX); in smu_feature_update_enable_state() 155 (unsigned long *)(&feature_mask), SMU_FEATURE_MAX); in smu_feature_update_enable_state() 164 uint32_t feature_mask[2] = { 0 }; in smu_sys_set_pp_feature_mask() local 171 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2); in smu_sys_set_pp_feature_mask() [all …]
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H A D | amdgpu_arcturus_ppt.c | 360 uint32_t *feature_mask, uint32_t num) in arcturus_get_allowed_feature_mask() argument 366 memset(feature_mask, 0xFF, sizeof(uint32_t) * num); in arcturus_get_allowed_feature_mask() 742 uint32_t feature_mask) in arcturus_upload_dpm_level() argument 751 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) { in arcturus_upload_dpm_level() 766 (feature_mask & FEATURE_DPM_UCLK_MASK)) { in arcturus_upload_dpm_level() 781 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) { in arcturus_upload_dpm_level() 1960 uint32_t feature_mask[2]; in arcturus_is_dpm_running() local 1962 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2); in arcturus_is_dpm_running() 1965 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] | in arcturus_is_dpm_running() 1966 ((uint64_t)feature_mask[1] << 32)); in arcturus_is_dpm_running()
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H A D | amdgpu_vega20_ppt.c | 603 uint32_t *feature_mask, uint32_t num) in vega20_get_allowed_feature_mask() argument 608 memset(feature_mask, 0, sizeof(uint32_t) * num); in vega20_get_allowed_feature_mask() 1194 uint32_t feature_mask) in vega20_upload_dpm_level() argument 1204 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) { in vega20_upload_dpm_level() 1219 (feature_mask & FEATURE_DPM_UCLK_MASK)) { in vega20_upload_dpm_level() 1234 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) { in vega20_upload_dpm_level() 1249 (feature_mask & FEATURE_DPM_FCLK_MASK)) { in vega20_upload_dpm_level() 1264 (feature_mask & FEATURE_DPM_DCEFCLK_MASK)) { in vega20_upload_dpm_level() 2849 uint32_t feature_mask[2]; in vega20_is_dpm_running() local 2851 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2); in vega20_is_dpm_running() [all …]
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H A D | smu_internal.h | 161 #define smu_get_allowed_feature_mask(smu, feature_mask, num) \ argument 162 …owed_feature_mask? (smu)->ppt_funcs->get_allowed_feature_mask((smu), (feature_mask), (num)) : 0) :…
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H A D | amdgpu_amd_powerplay.c | 61 hwmgr->feature_mask = adev->pm.pp_feature; in amd_powerplay_create()
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/netbsd/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/ |
H A D | vega10_smumgr.h | 48 bool enable, uint32_t feature_mask);
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H A D | vega12_smumgr.h | 54 bool enable, uint64_t feature_mask);
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H A D | amdgpu_vega12_smumgr.c | 126 bool enable, uint64_t feature_mask) in vega12_enable_smc_features() argument 130 smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT); in vega12_enable_smc_features() 131 smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT); in vega12_enable_smc_features()
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H A D | vega20_smumgr.h | 53 bool enable, uint64_t feature_mask);
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H A D | amdgpu_vega20_smumgr.c | 313 bool enable, uint64_t feature_mask) in vega20_enable_smc_features() argument 318 smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT); in vega20_enable_smc_features() 319 smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT); in vega20_enable_smc_features()
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H A D | amdgpu_vega10_smumgr.c | 112 bool enable, uint32_t feature_mask) in vega10_enable_smc_features() argument 126 msg, feature_mask); in vega10_enable_smc_features()
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H A D | amdgpu_smu7_smumgr.c | 590 (hwmgr->feature_mask & PP_AVFS_MASK)) in smu7_init()
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/netbsd/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
H A D | smu_v12_0.h | 81 uint32_t *feature_mask, uint32_t num);
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H A D | smu_v11_0.h | 196 uint32_t *feature_mask, uint32_t num);
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H A D | amdgpu_smu.h | 425 int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num); 523 int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
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H A D | hwmgr.h | 791 uint32_t feature_mask; member
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/netbsd/sys/external/bsd/ena-com/ |
H A D | ena_com.c | 892 u32 feature_mask = 1 << feature_id; in ena_com_check_supported_feature_id() local 896 !(ena_dev->supported_features & feature_mask)) in ena_com_check_supported_feature_id()
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