Home
last modified time | relevance | path

Searched refs:lane_width (Results 1 – 10 of 10) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
H A Dhwmgr_ppt.h99 uint8_t lane_width; member
H A Damdgpu_vega20_hwmgr.c3277 uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; in vega20_print_clock_levels() local
3374 lane_width = data->pcie_width_level1; in vega20_print_clock_levels()
3377 lane_width = pptable->PcieLaneCount[i]; in vega20_print_clock_levels()
3384 (lane_width == 1) ? "x1" : in vega20_print_clock_levels()
3385 (lane_width == 2) ? "x2" : in vega20_print_clock_levels()
3386 (lane_width == 3) ? "x4" : in vega20_print_clock_levels()
3387 (lane_width == 4) ? "x8" : in vega20_print_clock_levels()
3388 (lane_width == 5) ? "x12" : in vega20_print_clock_levels()
3389 (lane_width == 6) ? "x16" : "", in vega20_print_clock_levels()
3392 (current_lane_width == lane_width) ? in vega20_print_clock_levels()
H A Damdgpu_process_pptables_v1_0.c542 pcie_record->lane_width = le16_to_cpu(atom_pcie_record->usPCIELaneWidth); in get_pcie_table()
582 pcie_record->lane_width = le16_to_cpu(atom_pcie_record->usPCIELaneWidth); in get_pcie_table()
H A Damdgpu_vega10_processpptables.c848 pcie_table->entries[i].lane_width = in get_pcie_table()
H A Damdgpu_smu7_hwmgr.c577 pcie_table->entries[i].lane_width)); in smu7_setup_default_pcie_table()
H A Damdgpu_vega10_hwmgr.c1279 bios_pcie_table->entries[i].lane_width); in vega10_setup_default_pcie_table()
/netbsd/sys/external/bsd/drm2/dist/drm/amd/powerplay/
H A Damdgpu_navi10_ppt.c772 uint32_t gen_speed, lane_width; in navi10_print_clk_levels() local
835 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & in navi10_print_clk_levels()
852 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? in navi10_print_clk_levels()
H A Damdgpu_vega20_ppt.c955 uint32_t gen_speed, lane_width; in vega20_print_clk_levels() local
1073 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & in vega20_print_clk_levels()
1090 (lane_width == pptable->PcieLaneCount[i]) ? in vega20_print_clk_levels()
/netbsd/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_si_dpm.c4705 u32 lane_width; in si_init_smc_table() local
4774 lane_width = radeon_get_pcie_lanes(rdev); in si_init_smc_table()
4775 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_init_smc_table()
5921 u32 lane_width; in si_set_pcie_lane_width_in_smc() local
5929 lane_width = radeon_get_pcie_lanes(rdev); in si_set_pcie_lane_width_in_smc()
5930 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_set_pcie_lane_width_in_smc()
/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_si_dpm.c5169 u32 lane_width; in si_init_smc_table() local
5238 lane_width = amdgpu_get_pcie_lanes(adev); in si_init_smc_table()
5239 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_init_smc_table()
6381 u32 lane_width; in si_set_pcie_lane_width_in_smc() local
6389 lane_width = amdgpu_get_pcie_lanes(adev); in si_set_pcie_lane_width_in_smc()
6390 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_set_pcie_lane_width_in_smc()