Searched refs:mmCGTS_CU5_SP0_CTRL_REG (Results 1 – 9 of 9) sorted by relevance
| /netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_mxgpu_vi.c | 200 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
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| H A D | amdgpu_gfx_v8_0.c | 294 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
568 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
664 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/ |
| H A D | gfx_7_0_d.h | 1512 #define mmCGTS_CU5_SP0_CTRL_REG 0xf021 macro
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| H A D | gfx_7_2_d.h | 1533 #define mmCGTS_CU5_SP0_CTRL_REG 0xf021 macro
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| H A D | gfx_8_0_d.h | 1726 #define mmCGTS_CU5_SP0_CTRL_REG 0xf021 macro
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| H A D | gfx_8_1_d.h | 1694 #define mmCGTS_CU5_SP0_CTRL_REG 0xf021 macro
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_0_offset.h | 6360 #define mmCGTS_CU5_SP0_CTRL_REG … macro
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| H A D | gc_9_2_1_offset.h | 6594 #define mmCGTS_CU5_SP0_CTRL_REG … macro
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| H A D | gc_9_1_offset.h | 6582 #define mmCGTS_CU5_SP0_CTRL_REG … macro
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