Searched refs:mmCP_HQD_DEQUEUE_REQUEST (Results 1 – 16 of 16) sorted by relevance
| /netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_amdkfd_gfx_v8.c | 513 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST); in kgd_hqd_destroy()
528 WREG32(mmCP_HQD_DEQUEUE_REQUEST, type); in kgd_hqd_destroy()
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| H A D | amdgpu_amdkfd_gfx_v7.c | 515 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST); in kgd_hqd_destroy()
530 WREG32(mmCP_HQD_DEQUEUE_REQUEST, type); in kgd_hqd_destroy()
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| H A D | amdgpu_amdkfd_gfx_v10.c | 645 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST); in kgd_hqd_destroy()
661 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type); in kgd_hqd_destroy()
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| H A D | amdgpu_amdkfd_gfx_v9.c | 591 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type); in kgd_gfx_v9_hqd_destroy()
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| H A D | amdgpu_gfx_v9_0.c | 3488 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); in gfx_v9_0_kiq_init_register()
3494 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, in gfx_v9_0_kiq_init_register()
3577 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); in gfx_v9_0_kiq_fini_register()
3592 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, in gfx_v9_0_kiq_fini_register()
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| H A D | amdgpu_gfx_v7_0.c | 2918 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1); in gfx_v7_0_mqd_deactivate()
2928 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0); in gfx_v7_0_mqd_deactivate()
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| H A D | amdgpu_gfx_v10_0.c | 3381 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); in gfx_v10_0_kiq_init_register()
3387 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, in gfx_v10_0_kiq_init_register()
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| H A D | amdgpu_gfx_v8_0.c | 4425 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0); in gfx_v8_0_deactivate_hqd()
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/ |
| H A D | gfx_7_0_d.h | 593 #define mmCP_HQD_DEQUEUE_REQUEST 0x325d macro
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| H A D | gfx_7_2_d.h | 606 #define mmCP_HQD_DEQUEUE_REQUEST 0x325d macro
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| H A D | gfx_8_0_d.h | 656 #define mmCP_HQD_DEQUEUE_REQUEST 0x325d macro
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| H A D | gfx_8_1_d.h | 656 #define mmCP_HQD_DEQUEUE_REQUEST 0x325d macro
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_0_offset.h | 2862 #define mmCP_HQD_DEQUEUE_REQUEST … macro
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| H A D | gc_9_2_1_offset.h | 3046 #define mmCP_HQD_DEQUEUE_REQUEST … macro
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| H A D | gc_9_1_offset.h | 3090 #define mmCP_HQD_DEQUEUE_REQUEST … macro
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| H A D | gc_10_1_0_offset.h | 5328 #define mmCP_HQD_DEQUEUE_REQUEST … macro
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