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Searched refs:mmDC_EDC_STATE_CNT (Results 1 – 6 of 6) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_1_offset.h129 #define mmDC_EDC_STATE_CNT … macro
H A Dgc_9_0_offset.h2648 #define mmDC_EDC_STATE_CNT … macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_gfx_v9_4.c50 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1, 1 },
133 { "CPC_DC_STATE_RAM_ME1", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT),
H A Damdgpu_gfx_v9_0.c4125 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1, 1},
5681 { "DC_STATE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT),
H A Damdgpu_gfx_v8_0.c1506 mmDC_EDC_STATE_CNT,
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_d.h2824 #define mmDC_EDC_STATE_CNT 0x3191 macro