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Searched refs:mmGC_USER_SHADER_ARRAY_CONFIG (Results 1 – 14 of 14) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h694 #define mmGC_USER_SHADER_ARRAY_CONFIG 0x2270 macro
H A Dgfx_7_0_d.h2340 #define mmGC_USER_SHADER_ARRAY_CONFIG 0x2270 macro
H A Dgfx_7_2_d.h2364 #define mmGC_USER_SHADER_ARRAY_CONFIG 0x2270 macro
H A Dgfx_8_0_d.h2604 #define mmGC_USER_SHADER_ARRAY_CONFIG 0x2270 macro
H A Dgfx_8_1_d.h2583 #define mmGC_USER_SHADER_ARRAY_CONFIG 0x2270 macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_gfx_v6_0.c1533 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data); in gfx_v6_0_set_user_cu_inactive_bitmap()
1541 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); in gfx_v6_0_get_cu_enabled()
H A Damdgpu_gfx_v7_0.c3827 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data); in gfx_v7_0_set_user_cu_inactive_bitmap()
3835 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); in gfx_v7_0_get_cu_active_bitmap()
H A Damdgpu_gfx_v10_0.c5352 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); in gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh()
5359 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); in gfx_v10_0_get_wgp_active_bitmap_per_sh()
H A Damdgpu_gfx_v9_0.c6678 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); in gfx_v9_0_set_user_cu_inactive_bitmap()
6686 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); in gfx_v9_0_get_cu_active_bitmap()
H A Damdgpu_gfx_v8_0.c7086 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data); in gfx_v8_0_set_user_cu_inactive_bitmap()
7094 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); in gfx_v8_0_get_cu_active_bitmap()
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h318 #define mmGC_USER_SHADER_ARRAY_CONFIG … macro
H A Dgc_9_2_1_offset.h308 #define mmGC_USER_SHADER_ARRAY_CONFIG … macro
H A Dgc_9_1_offset.h314 #define mmGC_USER_SHADER_ARRAY_CONFIG … macro
H A Dgc_10_1_0_offset.h2342 #define mmGC_USER_SHADER_ARRAY_CONFIG … macro