Home
last modified time | relevance | path

Searched refs:mmRLC_CNTL (Results 1 – 15 of 15) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
H A Dpolaris10_pwrvirus.h51 { 0x00000000, mmRLC_CNTL },
/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_gfx_v6_0.c2465 tmp = RREG32(mmRLC_CNTL); in gfx_v6_0_update_rlc()
2467 WREG32(mmRLC_CNTL, rlc); in gfx_v6_0_update_rlc()
2474 orig = data = RREG32(mmRLC_CNTL); in gfx_v6_0_halt_rlc()
2478 WREG32(mmRLC_CNTL, data); in gfx_v6_0_halt_rlc()
2488 WREG32(mmRLC_CNTL, 0); in gfx_v6_0_rlc_stop()
2496 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); in gfx_v6_0_rlc_start()
H A Damdgpu_gfx_v7_0.c3406 tmp = RREG32(mmRLC_CNTL); in gfx_v7_0_update_rlc()
3408 WREG32(mmRLC_CNTL, rlc); in gfx_v7_0_update_rlc()
3415 orig = data = RREG32(mmRLC_CNTL); in gfx_v7_0_halt_rlc()
3421 WREG32(mmRLC_CNTL, data); in gfx_v7_0_halt_rlc()
3479 WREG32(mmRLC_CNTL, 0); in gfx_v7_0_rlc_stop()
3495 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); in gfx_v7_0_rlc_start()
H A Damdgpu_gfx_v10_0.c1804 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); in gfx_v10_0_rlc_stop()
1807 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); in gfx_v10_0_rlc_stop()
2193 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); in gfx_v10_0_rlc_backdoor_autoload_enable()
4009 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); in gfx_v10_0_is_rlc_enabled()
H A Damdgpu_gfx_v8_0.c5549 rlc_setting = RREG32(mmRLC_CNTL); in gfx_v8_0_is_rlc_enabled()
5560 data = RREG32(mmRLC_CNTL); in gfx_v8_0_set_safe_mode()
5588 data = RREG32(mmRLC_CNTL); in gfx_v8_0_unset_safe_mode()
H A Damdgpu_gfx_v9_0.c4442 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL); in gfx_v9_0_is_rlc_enabled()
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h1138 #define mmRLC_CNTL 0x30C0 macro
H A Dgfx_7_0_d.h1242 #define mmRLC_CNTL 0x30c0 macro
H A Dgfx_7_2_d.h1255 #define mmRLC_CNTL 0x30c0 macro
H A Dgfx_8_0_d.h1344 #define mmRLC_CNTL 0xec00 macro
H A Dgfx_8_1_d.h1347 #define mmRLC_CNTL 0xec00 macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h5960 #define mmRLC_CNTL … macro
H A Dgc_9_2_1_offset.h6146 #define mmRLC_CNTL … macro
H A Dgc_9_1_offset.h6182 #define mmRLC_CNTL … macro
H A Dgc_10_1_0_offset.h9270 #define mmRLC_CNTL … macro