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Searched refs:mmSPI_WCL_PIPE_PERCENT_GFX (Results 1 – 10 of 10) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h1412 #define mmSPI_WCL_PIPE_PERCENT_GFX 0x31c7 macro
H A Dgfx_7_2_d.h1429 #define mmSPI_WCL_PIPE_PERCENT_GFX 0x31c7 macro
H A Dgfx_8_0_d.h1608 #define mmSPI_WCL_PIPE_PERCENT_GFX 0x31c7 macro
H A Dgfx_8_1_d.h1576 #define mmSPI_WCL_PIPE_PERCENT_GFX 0x31c7 macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2692 #define mmSPI_WCL_PIPE_PERCENT_GFX … macro
H A Dgc_9_2_1_offset.h2878 #define mmSPI_WCL_PIPE_PERCENT_GFX … macro
H A Dgc_9_1_offset.h2936 #define mmSPI_WCL_PIPE_PERCENT_GFX … macro
H A Dgc_10_1_0_offset.h5172 #define mmSPI_WCL_PIPE_PERCENT_GFX … macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_gfx_v9_0.c5066 reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX) + pipe_num; in gfx_v9_0_ring_set_pipe_percent()
H A Damdgpu_gfx_v8_0.c6260 reg = mmSPI_WCL_PIPE_PERCENT_GFX + pipe_num; in gfx_v8_0_ring_set_pipe_percent()