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Searched refs:mmUVD_SUVD_CGC_CTRL (Results 1 – 12 of 12) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
H A Duvd_5_0_d.h93 #define mmUVD_SUVD_CGC_CTRL 0x3be6 macro
H A Duvd_6_0_d.h109 #define mmUVD_SUVD_CGC_CTRL 0x3be6 macro
H A Duvd_7_0_offset.h70 #define mmUVD_SUVD_CGC_CTRL … macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_vcn_v2_0.c542 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); in vcn_v2_0_disable_clock_gating()
553 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); in vcn_v2_0_disable_clock_gating()
601 UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); in vcn_v2_0_clock_gating_dpg_mode()
649 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); in vcn_v2_0_enable_clock_gating()
660 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); in vcn_v2_0_enable_clock_gating()
H A Damdgpu_uvd_v5_0.c658 data2 = RREG32(mmUVD_SUVD_CGC_CTRL); in uvd_v5_0_set_sw_clock_gating()
697 WREG32(mmUVD_SUVD_CGC_CTRL, data2); in uvd_v5_0_set_sw_clock_gating()
H A Damdgpu_vcn_v1_0.c549 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
560 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); in vcn_v1_0_disable_clock_gating()
622 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); in vcn_v1_0_enable_clock_gating()
633 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); in vcn_v1_0_enable_clock_gating()
687 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
H A Damdgpu_vcn_v2_5.c632 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL); in vcn_v2_5_disable_clock_gating()
643 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data); in vcn_v2_5_disable_clock_gating()
692 UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
742 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL); in vcn_v2_5_enable_clock_gating()
753 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data); in vcn_v2_5_enable_clock_gating()
H A Damdgpu_uvd_v6_0.c1313 data2 = RREG32(mmUVD_SUVD_CGC_CTRL); in uvd_v6_0_set_sw_clock_gating()
1353 WREG32(mmUVD_SUVD_CGC_CTRL, data2); in uvd_v6_0_set_sw_clock_gating()
H A Damdgpu_uvd_v7_0.c1594 data2 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL);
1641 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL, data2);
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h160 #define mmUVD_SUVD_CGC_CTRL … macro
H A Dvcn_2_5_offset.h511 #define mmUVD_SUVD_CGC_CTRL … macro
H A Dvcn_2_0_0_offset.h824 #define mmUVD_SUVD_CGC_CTRL … macro