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Searched refs:mmUVD_SUVD_CGC_GATE (Results 1 – 12 of 12) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_uvd_v5_0.c611 data1 = RREG32(mmUVD_SUVD_CGC_GATE); in uvd_v5_0_enable_clock_gating()
649 WREG32(mmUVD_SUVD_CGC_GATE, data1); in uvd_v5_0_enable_clock_gating()
706 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
737 WREG32(mmUVD_SUVD_CGC_GATE, data1);
H A Damdgpu_uvd_v6_0.c625 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
693 WREG32(mmUVD_SUVD_CGC_GATE, data1);
1257 data1 = RREG32(mmUVD_SUVD_CGC_GATE); in uvd_v6_0_enable_clock_gating()
1304 WREG32(mmUVD_SUVD_CGC_GATE, data1); in uvd_v6_0_enable_clock_gating()
1362 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
1395 WREG32(mmUVD_SUVD_CGC_GATE, data1);
H A Damdgpu_uvd_v7_0.c1593 data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1640 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
1649 data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1682 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
H A Damdgpu_vcn_v2_0.c515 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); in vcn_v2_0_disable_clock_gating()
540 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data); in vcn_v2_0_disable_clock_gating()
597 UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); in vcn_v2_0_clock_gating_dpg_mode()
H A Damdgpu_vcn_v1_0.c522 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); in vcn_v1_0_disable_clock_gating()
547 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data); in vcn_v1_0_disable_clock_gating()
684 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
H A Damdgpu_vcn_v2_5.c605 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE); in vcn_v2_5_disable_clock_gating()
630 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE, data); in vcn_v2_5_disable_clock_gating()
688 UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
H A Duvd_5_0_d.h91 #define mmUVD_SUVD_CGC_GATE 0x3be4 macro
H A Duvd_6_0_d.h107 #define mmUVD_SUVD_CGC_GATE 0x3be4 macro
H A Duvd_7_0_offset.h68 #define mmUVD_SUVD_CGC_GATE … macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h156 #define mmUVD_SUVD_CGC_GATE … macro
H A Dvcn_2_5_offset.h507 #define mmUVD_SUVD_CGC_GATE … macro
H A Dvcn_2_0_0_offset.h820 #define mmUVD_SUVD_CGC_GATE … macro