Searched refs:mmVCE_UENC_CLOCK_GATING (Results 1 – 7 of 7) sorted by relevance
| /netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_vce_v2_0.c | 162 tmp = RREG32(mmVCE_UENC_CLOCK_GATING); in vce_v2_0_init_cg()
165 WREG32(mmVCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_init_cg()
178 WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); in vce_v2_0_mc_resume()
324 tmp = RREG32(mmVCE_UENC_CLOCK_GATING); in vce_v2_0_set_sw_cg()
326 WREG32(mmVCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
339 tmp = RREG32(mmVCE_UENC_CLOCK_GATING); in vce_v2_0_set_sw_cg()
342 WREG32(mmVCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
370 orig = tmp = RREG32(mmVCE_UENC_CLOCK_GATING); in vce_v2_0_set_dyn_cg()
374 WREG32(mmVCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_set_dyn_cg()
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| H A D | amdgpu_vce_v3_0.c | 192 data = RREG32(mmVCE_UENC_CLOCK_GATING); in vce_v3_0_set_vce_sw_clock_gating()
195 WREG32(mmVCE_UENC_CLOCK_GATING, data); in vce_v3_0_set_vce_sw_clock_gating()
218 data = RREG32(mmVCE_UENC_CLOCK_GATING); in vce_v3_0_set_vce_sw_clock_gating()
220 WREG32(mmVCE_UENC_CLOCK_GATING, data); in vce_v3_0_set_vce_sw_clock_gating()
534 WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); in vce_v3_0_mc_resume()
769 data = RREG32(mmVCE_UENC_CLOCK_GATING); in vce_v3_0_set_clockgating_state()
772 WREG32(mmVCE_UENC_CLOCK_GATING, data); in vce_v3_0_set_clockgating_state()
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| H A D | amdgpu_vce_v4_0.c | 615 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING), 0x1FF000, ~0xFF9FF000); in vce_v4_0_mc_resume()
833 data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING));
836 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING), data);
859 data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING));
861 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING), data);
924 data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING);
927 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING, data);
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vce/ |
| H A D | vce_1_0_d.h | 55 #define mmVCE_UENC_CLOCK_GATING 0x816F macro
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| H A D | vce_2_0_d.h | 53 #define mmVCE_UENC_CLOCK_GATING 0x81ef macro
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| H A D | vce_3_0_d.h | 57 #define mmVCE_UENC_CLOCK_GATING 0x81ef macro
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| H A D | vce_4_0_offset.h | 118 #define mmVCE_UENC_CLOCK_GATING … macro
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