Searched refs:queue_mask (Results 1 – 9 of 9) sorted by relevance
493 uint64_t queue_mask = 0; in amdgpu_gfx_enable_kcq() local506 if (WARN_ON(i > (sizeof(queue_mask)*8))) { in amdgpu_gfx_enable_kcq()511 queue_mask |= (1ull << i); in amdgpu_gfx_enable_kcq()525 kiq->pmf->kiq_set_resources(kiq_ring, queue_mask); in amdgpu_gfx_enable_kcq()
70 uint64_t queue_mask);
4353 uint64_t queue_mask = 0; in gfx_v8_0_kiq_kcq_enable() local4363 if (WARN_ON(i >= (sizeof(queue_mask)*8))) { in gfx_v8_0_kiq_kcq_enable()4368 queue_mask |= (1ull << i); in gfx_v8_0_kiq_kcq_enable()4379 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ in gfx_v8_0_kiq_kcq_enable()4380 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ in gfx_v8_0_kiq_kcq_enable()
268 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) in gfx10_kiq_set_resources() argument273 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ in gfx10_kiq_set_resources()274 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ in gfx10_kiq_set_resources()
753 uint64_t queue_mask) in gfx_v9_0_kiq_set_resources() argument761 lower_32_bits(queue_mask)); /* queue mask lo */ in gfx_v9_0_kiq_set_resources()763 upper_32_bits(queue_mask)); /* queue mask hi */ in gfx_v9_0_kiq_set_resources()
141 packet->queue_mask_lo = lower_32_bits(res->queue_mask); in pm_set_resources_v9()142 packet->queue_mask_hi = upper_32_bits(res->queue_mask); in pm_set_resources_v9()
140 packet->queue_mask_lo = lower_32_bits(res->queue_mask); in pm_set_resources_vi()141 packet->queue_mask_hi = upper_32_bits(res->queue_mask); in pm_set_resources_vi()
1032 res.queue_mask = 0; in set_sched_resources()1048 if (WARN_ON(i >= (sizeof(res.queue_mask)*8))) { in set_sched_resources()1053 res.queue_mask |= (1ull << i); in set_sched_resources()1061 res.vmid_mask, res.queue_mask); in set_sched_resources()
529 uint64_t queue_mask; member