/openbsd/gnu/llvm/llvm/lib/Target/Mips/ |
H A D | MipsAnalyzeImmediate.cpp | 35 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL)); in GetInstSeqLsADDiu() 61 AddInstr(SeqLs, Inst(ADDiu, MaskedImm)); in GetInstSeqLs() 92 if ((Seq.size() < 2) || (Seq[0].Opc != ADDiu) || in ReplaceADDiuSLLWithLUi() 134 ADDiu = Mips::ADDiu; in Analyze() 139 ADDiu = Mips::DADDiu; in Analyze()
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H A D | MipsInstructionSelector.cpp | 163 B.buildInstr(Mips::ADDiu, {DestReg}, {Register(Mips::ZERO)}) in materialize32BitImm() 354 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) in select() 692 MachineInstr *ADDiu = in select() local 693 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) in select() 697 ADDiu->getOperand(2).setTargetFlags(MipsII::MO_ABS_LO); in select() 698 if (!constrainSelectedInstRegOperands(*ADDiu, TII, TRI, RBI)) in select() 711 MachineInstr *ADDiu = in select() local 712 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) in select() 716 ADDiu->getOperand(2).setTargetFlags(MipsII::MO_ABS_LO); in select() 717 if (!constrainSelectedInstRegOperands(*ADDiu, TII, TRI, RBI)) in select() [all …]
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H A D | MipsAnalyzeImmediate.h | 60 unsigned ADDiu, ORi, SLL, LUi; variable
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H A D | MipsMachineFunction.cpp | 110 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0) in initGlobalBaseReg() 126 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1) in initGlobalBaseReg()
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H A D | MipsBranchExpansion.cpp | 470 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch() 531 BuildMI(*BalTgtMBB, std::prev(Pos), DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch() 539 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch() 739 BuildMI(MBB, I, DL, TII->get(Mips::ADDiu), Mips::V0) in emitGPDisp()
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H A D | Relocation.txt | 65 defm : MipsHiLoRelocs<LUi, ADDiu, ZERO, GPR32Opnd>;
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H A D | MipsMCInstLower.cpp | 306 lowerLongBranchADDiu(MI, OutMI, Mips::ADDiu); in lowerLongBranch()
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H A D | MipsInstrInfo.td | 123 // target constant nodes that would otherwise remain unchanged with ADDiu 2903 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs, 3161 defm : MaterializeImms<i32, ZERO, ADDiu, LUi, ORi>, ISA_MIPS1; 3171 (ADDiu GPR32:$src, imm:$imm)>, ISA_MIPS1, ASE_NOT_DSP; 3237 defm : MipsHiLoRelocs<LUi, ADDiu, ZERO, GPR32Opnd>, ISA_MIPS1; 3252 def : WrapperPat<tglobaladdr, ADDiu, GPR32>, ISA_MIPS1; 3253 def : WrapperPat<tconstpool, ADDiu, GPR32>, ISA_MIPS1; 3254 def : WrapperPat<texternalsym, ADDiu, GPR32>, ISA_MIPS1; 3255 def : WrapperPat<tblockaddress, ADDiu, GPR32>, ISA_MIPS1; 3256 def : WrapperPat<tjumptable, ADDiu, GPR32>, ISA_MIPS1; [all …]
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H A D | MicroMipsSizeReduction.cpp | 214 {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUR1SP_MM), 216 {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUSP_MM), ReduceADDIUToADDIUSP,
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H A D | MipsSEISelDAGToDAG.cpp | 88 if ((MI.getOpcode() == Mips::ADDiu) && in replaceUsesWithZeroReg() 146 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Mips::ADDiu)) in emitMCountABI() 1146 const unsigned ADDiuOp = Is32BitSplat ? Mips::ADDiu : Mips::DADDiu; in trySelect()
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H A D | MipsFastISel.cpp | 364 unsigned Opc = Mips::ADDiu; in materialize32BitInt() 423 emitInst(Mips::ADDiu, TempReg) in materializeGV() 738 emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0); in emitCmp() 739 emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1); in emitCmp()
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H A D | MipsSEFrameLowering.cpp | 418 unsigned ADDiu = ABI.GetPtrAddiuOp(); in emitPrologue() local 546 BuildMI(MBB, MBBI, dl, TII.get(ADDiu), VR).addReg(ZERO).addImm(MaxAlign); in emitPrologue()
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H A D | MipsSEInstrInfo.cpp | 594 unsigned ADDiu = ABI.GetPtrAddiuOp(); in adjustStackPtr() local 601 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount); in adjustStackPtr()
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H A D | MipsInstrInfo.cpp | 974 case Mips::ADDiu: in isAddImmediate()
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H A D | MipsAsmPrinter.cpp | 1306 MCInstBuilder(Mips::ADDiu) in EmitSled()
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H A D | MipsSEISelLowering.cpp | 3059 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2) in emitBPOSGE32() 3065 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1) in emitBPOSGE32() 3128 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1) in emitMSACBranchPseudo() 3134 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2) in emitMSACBranchPseudo()
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H A D | MipsDSPInstrInfo.td | 1392 (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR)), 1400 (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR))))>;
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H A D | MipsScheduleP5600.td | 224 def : InstRW<[P5600WriteEitherALU], (instrs ADD, ADDi, ADDiu, ANDi, ORi, ROTR,
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H A D | Mips64InstrInfo.td | 910 (ADDiu GPR32:$src, immSExt16:$imm16), sub_32)>;
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H A D | MipsScheduleGeneric.td | 47 def : InstRW<[GenericWriteALU], (instrs ADD, ADDi, ADDiu, ADDu, AND, ANDi,
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H A D | MipsISelLowering.cpp | 1972 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2) in emitAtomicCmpSwapPartword()
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/openbsd/gnu/llvm/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsABIInfo.cpp | 109 return ArePtrs64bit() ? Mips::DADDiu : Mips::ADDiu; in GetPtrAddiuOp()
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H A D | MipsTargetStreamer.cpp | 1188 TmpInst.setOpcode(Mips::ADDiu); in emitDirectiveCpLoad() 1271 emitRRX(Mips::ADDiu, GPReg, GPReg, MCOperand::createExpr(LoExpr), SMLoc(), in emitDirectiveCpsetup() 1288 emitRRX(Mips::ADDiu, GPReg, GPReg, MCOperand::createExpr(LoExpr), SMLoc(), in emitDirectiveCpsetup()
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/openbsd/gnu/llvm/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 2561 case Mips::ADDiu: case Mips::ADDiu_MM: in tryExpandInstruction() 2760 TOut.emitRRI(Mips::ADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI); in loadImmediate() 3010 TOut.emitRRX(IsPtr64 ? Mips::DADDiu : Mips::ADDiu, TmpReg, TmpReg, in loadAndAddSymbolAddress() 3077 TOut.emitRRX(IsPtr64 ? Mips::DADDiu : Mips::ADDiu, TmpReg, TmpReg, in loadAndAddSymbolAddress() 3216 TOut.emitRRX(Mips::ADDiu, TmpReg, TmpReg, MCOperand::createExpr(LoExpr), in loadAndAddSymbolAddress() 3523 TOut.emitRRX(isABI_N64() ? Mips::DADDiu : Mips::ADDiu, TmpReg, TmpReg, in expandLoadDoubleImmToGPR() 4344 TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, -1, IDLoc, STI); in expandDivRem() 4355 TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, 1, IDLoc, STI); in expandDivRem() 4827 case Mips::ADDiu: in expandAliasImmediate() 5456 Opc = isGP64bit() ? Mips::DADDiu : Mips::ADDiu; in expandSeqI() [all …]
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