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Searched refs:CP_MEC_CNTL__MEC_ME1_HALT_MASK (Results 1 – 17 of 17) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Dgfx_v7_0.c2634 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | in gfx_v7_0_cp_compute_enable()
4625 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK); in gfx_v7_0_soft_reset()
H A Dgfx_v9_4_3.c1388 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); in gfx_v9_4_3_xcc_cp_compute_enable()
H A Dgfx_v10_0.c6214 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | in gfx_v10_0_cp_compute_enable()
6219 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | in gfx_v10_0_cp_compute_enable()
H A Dgfx_v8_0.c4295 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); in gfx_v8_0_cp_compute_enable()
H A Dgfx_v9_0.c3172 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); in gfx_v9_0_cp_compute_enable()
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h2225 #define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000 macro
H A Dgfx_8_0_sh_mask.h2771 #define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000 macro
H A Dgfx_8_1_sh_mask.h3293 #define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000 macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h848 #define CP_MEC_CNTL__MEC_ME1_HALT_MASK … macro
H A Dgc_9_1_sh_mask.h747 #define CP_MEC_CNTL__MEC_ME1_HALT_MASK … macro
H A Dgc_9_2_1_sh_mask.h736 #define CP_MEC_CNTL__MEC_ME1_HALT_MASK … macro
H A Dgc_9_4_3_sh_mask.h786 #define CP_MEC_CNTL__MEC_ME1_HALT_MASK … macro
H A Dgc_9_4_2_sh_mask.h1369 #define CP_MEC_CNTL__MEC_ME1_HALT_MASK … macro
H A Dgc_11_0_0_sh_mask.h24000 #define CP_MEC_CNTL__MEC_ME1_HALT_MASK … macro
H A Dgc_10_1_0_sh_mask.h6327 #define CP_MEC_CNTL__MEC_ME1_HALT_MASK … macro
H A Dgc_11_0_3_sh_mask.h26346 #define CP_MEC_CNTL__MEC_ME1_HALT_MASK … macro
H A Dgc_10_3_0_sh_mask.h6900 #define CP_MEC_CNTL__MEC_ME1_HALT_MASK … macro