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Searched refs:DCCG_AUDIO_DTO1_PHASE (Results 1 – 11 of 11) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/display/dc/dce/
H A Ddce_audio.h40 SR(DCCG_AUDIO_DTO1_PHASE)
57 SF(DCCG_AUDIO_DTO1_PHASE, DCCG_AUDIO_DTO1_PHASE, mask_sh),\
74 SF(DCCG_AUDIO_DTO1_PHASE, DCCG_AUDIO_DTO1_PHASE, mask_sh),\
94 uint32_t DCCG_AUDIO_DTO1_PHASE; member
112 uint8_t DCCG_AUDIO_DTO1_PHASE; member
132 uint32_t DCCG_AUDIO_DTO1_PHASE; member
H A Ddce_audio.c866 REG_UPDATE(DCCG_AUDIO_DTO1_PHASE, in dce_aud_wall_dto_setup()
867 DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase); in dce_aud_wall_dto_setup()
958 REG_UPDATE(DCCG_AUDIO_DTO1_PHASE, in dce60_aud_wall_dto_setup()
959 DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase); in dce60_aud_wall_dto_setup()
/openbsd/sys/dev/pci/drm/radeon/
H A Ddce3_1_afmt.c164 WREG32(DCCG_AUDIO_DTO1_PHASE, dto_phase); in dce3_2_audio_set_dto()
H A Ddce6_afmt.c316 WREG32(DCCG_AUDIO_DTO1_PHASE, 24000); in dce6_dp_audio_set_dto()
H A Devergreen_hdmi.c303 WREG32(DCCG_AUDIO_DTO1_PHASE, 24000); in dce4_dp_audio_set_dto()
H A Dr600_hdmi.c335 WREG32(DCCG_AUDIO_DTO1_PHASE, 24000 * 100); in r600_hdmi_audio_set_dto()
H A Dsid.h915 #define DCCG_AUDIO_DTO1_PHASE 0x05c0 macro
H A Devergreend.h508 #define DCCG_AUDIO_DTO1_PHASE 0x05c0 macro
H A Dr600d.h962 #define DCCG_AUDIO_DTO1_PHASE 0x0524 macro
/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Dsid.h918 #define DCCG_AUDIO_DTO1_PHASE 0x05c0 macro
/openbsd/sys/dev/pci/drm/amd/display/dc/dcn32/
H A Ddcn32_resource.h223 SR_ARR(DCCG_AUDIO_DTO1_PHASE, id) \