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Searched refs:DCE_HWIP (Results 1 – 9 of 9) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Ddimgrey_cavefish_reg_init.c44 adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCN_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
H A Dvega10_reg_init.c45 adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCE_BASE.instance[i])); in vega10_reg_base_init()
H A Dvega20_reg_init.c44 adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCE_BASE.instance[i])); in vega20_reg_base_init()
H A Dgmc_v9_0.c1388 switch (adev->ip_versions[DCE_HWIP][0]) { in gmc_v9_0_get_vbios_fb_size()
1836 if ((adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 0)) || in gmc_v9_0_save_registers()
1837 (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 1))) in gmc_v9_0_save_registers()
2286 if ((adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 0)) || in gmc_v9_0_restore_registers()
2287 (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 1))) { in gmc_v9_0_restore_registers()
H A Damdgpu_discovery.c196 [DCE_HWIP] = DMU_HWID,
1891 if (adev->ip_versions[DCE_HWIP][0]) { in amdgpu_discovery_set_display_ip_blocks()
1892 switch (adev->ip_versions[DCE_HWIP][0]) { in amdgpu_discovery_set_display_ip_blocks()
1918 adev->ip_versions[DCE_HWIP][0]); in amdgpu_discovery_set_display_ip_blocks()
2240 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1); in amdgpu_discovery_set_ip_blocks()
2256 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0); in amdgpu_discovery_set_ip_blocks()
H A Damdgpu.h662 DCE_HWIP, enumerator
H A Damdgpu_device.c6260 if (!adev->ip_versions[DCE_HWIP][0] || in amdgpu_device_has_display_hardware()
/openbsd/sys/dev/pci/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_plane.c1076 if (((adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 0)) || in amdgpu_dm_plane_fill_dc_scaling_info()
1077 (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 1))) && in amdgpu_dm_plane_fill_dc_scaling_info()
1517 if (dm->adev->ip_versions[DCE_HWIP][0] > IP_VERSION(3, 0, 1) && in amdgpu_dm_plane_init()
H A Damdgpu_dm.c1173 switch (adev->ip_versions[DCE_HWIP][0]) { in dm_dmub_hw_init()
1609 switch (adev->ip_versions[DCE_HWIP][0]) { in amdgpu_dm_init()
1634 switch (adev->ip_versions[DCE_HWIP][0]) { in amdgpu_dm_init()
2008 switch (adev->ip_versions[DCE_HWIP][0]) { in load_dmcu_fw()
2097 switch (adev->ip_versions[DCE_HWIP][0]) { in dm_dmub_sw_init()
2468 switch (adev->ip_versions[DCE_HWIP][0]) { in amdgpu_dm_smu_write_watermarks_table()
4444 switch (adev->ip_versions[DCE_HWIP][0]) { in amdgpu_dm_initialize_drm_device()
4461 adev->ip_versions[DCE_HWIP][0]); in amdgpu_dm_initialize_drm_device()
4607 adev->ip_versions[DCE_HWIP][0]); in amdgpu_dm_initialize_drm_device()
4690 switch (adev->ip_versions[DCE_HWIP][0]) { in dm_init_microcode()
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