| /openbsd/gnu/llvm/llvm/lib/Target/Mips/ |
| H A D | MipsCondMov.td | 20 InstSE<(outs DRC:$rd), (ins DRC:$rs, CRC:$rt, DRC:$F),
28 InstSE<(outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F),
60 (MOVZInst DRC:$T, (SLTOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
72 DRC:$T, DRC:$F),
75 DRC:$T, DRC:$F),
84 def : MipsPat<(select (i32 (seteq CRC:$lhs, 0)), DRC:$T, DRC:$F),
85 (MOVZInst DRC:$T, CRC:$lhs, DRC:$F)>;
99 def : MipsPat<(select CRC:$cond, DRC:$T, DRC:$F),
100 (MOVNInst DRC:$T, CRC:$cond, DRC:$F)>;
101 def : MipsPat<(select (i32 (setne CRC:$lhs, 0)),DRC:$T, DRC:$F),
[all …]
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| H A D | MipsInstrFPU.td | 216 class LWXC1_FT<string opstr, RegisterOperand DRC,
218 InstSE<(outs DRC:$fd), (ins PtrRC:$base, PtrRC:$index),
220 [(set DRC:$fd, (OpNode (add iPTR:$base, iPTR:$index)))], Itin,
225 class SWXC1_FT<string opstr, RegisterOperand DRC,
227 InstSE<(outs), (ins DRC:$fs, PtrRC:$base, PtrRC:$index),
229 [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin,
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| H A D | MipsInstrInfo.td | 1808 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
1809 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
1810 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]> {
1827 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
1828 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
1829 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]> {
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| /openbsd/sys/arch/macppc/dev/ |
| H A D | tumbler.c | 220 u_char DRC[2]; member
370 sizeof tas3001_initdata.DRC, /* 0x02 */
434 DEQ_WRITE(sc, DEQ_DRC, tas3001_initdata.DRC); in tas3001_init()
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| H A D | snapper.c | 391 u_char DRC[6]; member
592 sizeof tas3004_initdata.DRC, /* 0x02 */
672 DEQ_WRITE(sc, DEQ_DRC, tas3004_initdata.DRC); in tas3004_init()
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| /openbsd/gnu/llvm/llvm/lib/Target/Hexagon/ |
| H A D | HexagonEarlyIfConv.cpp | 203 const TargetRegisterClass *DRC, unsigned PredR, unsigned TR,
778 MachineBasicBlock::iterator At, const TargetRegisterClass *DRC, in buildMux() argument
781 switch (DRC->getID()) { in buildMux()
802 Register MuxR = MRI->createVirtualRegister(DRC); in buildMux()
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| H A D | HexagonBitSimplify.cpp | 961 auto *DRC = getFinalVRegClass(RD, MRI); in isTransparentCopy() local
962 if (!DRC) in isTransparentCopy()
965 return DRC == getFinalVRegClass(RS, MRI); in isTransparentCopy()
1511 const BitTracker::RegisterCell &DRC = BT.lookup(DR); in processBlock() local
1512 if (HBS::getConst(DRC, 0, DRC.width(), U)) { in processBlock()
1519 BT.put(ImmReg, DRC); in processBlock()
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| /openbsd/gnu/llvm/llvm/lib/CodeGen/ |
| H A D | MachineVerifier.cpp | 2112 if (const TargetRegisterClass *DRC = in visitMachineOperand() local
2114 if (!DRC->contains(Reg)) { in visitMachineOperand()
2117 << TRI->getRegClassName(DRC) << " register.\n"; in visitMachineOperand()
2226 if (const TargetRegisterClass *DRC = in visitMachineOperand() local
2235 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx); in visitMachineOperand()
2236 if (!DRC) { in visitMachineOperand()
2241 if (!RC->hasSuperClassEq(DRC)) { in visitMachineOperand()
2243 errs() << "Expected a " << TRI->getRegClassName(DRC) in visitMachineOperand()
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| H A D | MachineSink.cpp | 283 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY() local
284 if (SRC != DRC) in INITIALIZE_PASS_DEPENDENCY()
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| /openbsd/gnu/llvm/llvm/lib/Target/AVR/ |
| H A D | AVRInstrInfo.td | 1457 class AtomicLoad<PatFrag Op, RegisterClass DRC, RegisterClass PTRRC>
1458 : Pseudo<(outs DRC
1462 "atomic_op", [(set DRC
1466 class AtomicStore<PatFrag Op, RegisterClass DRC, RegisterClass PTRRC>
1469 : $rd, DRC
1472 : $rd, DRC
1475 class AtomicLoadOp<PatFrag Op, RegisterClass DRC, RegisterClass PTRRC>
1476 : Pseudo<(outs DRC:$rd),
1477 (ins PTRRC:$rr, DRC:$operand),
1478 "atomic_op", [(set DRC:$rd, (Op i16:$rr, DRC:$operand))]>;
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| /openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 5063 const TargetRegisterClass *DRC = RI.getRegClass(OpInfo.RegClass); in isLegalRegOperand() local
5065 return DRC->contains(Reg); in isLegalRegOperand()
5075 DRC = RI.getMatchingSuperRegClass(SuperRC, DRC, MO.getSubReg()); in isLegalRegOperand()
5076 if (!DRC) in isLegalRegOperand()
5079 return RC->hasSuperClassEq(DRC); in isLegalRegOperand()
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