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Searched refs:FP32 (Results 1 – 13 of 13) sorted by relevance

/openbsd/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZInstrHFP.td22 def LTER : UnaryRR <"lter", 0x32, null_frag, FP32, FP32>;
89 def LCER : UnaryRR <"lcer", 0x33, null_frag, FP32, FP32>;
96 def LPER : UnaryRR <"lper", 0x30, null_frag, FP32, FP32>;
109 def HER : UnaryRR <"her", 0x34, null_frag, FP32, FP32>;
113 def SQER : UnaryRRE<"sqer", 0xB245, null_frag, FP32, FP32>;
121 def FIER : UnaryRRE<"fier", 0xB377, null_frag, FP32, FP32>;
133 def AER : BinaryRR<"aer", 0x3A, null_frag, FP32, FP32>;
144 def AUR : BinaryRR<"aur", 0x3E, null_frag, FP32, FP32>;
153 def SER : BinaryRR<"ser", 0x3B, null_frag, FP32, FP32>;
163 def SUR : BinaryRR<"sur", 0x3F, null_frag, FP32, FP32>;
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H A DSystemZInstrFP.td45 def LER : UnaryRR <"ler", 0x38, null_frag, FP32, FP32>;
51 def LDR32 : UnaryRR<"ldr", 0x28, null_frag, FP32, FP32>;
91 def CPSDRss : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP32, FP32, FP32>;
344 def LCDFR_32 : UnaryRRE<"lcdfr", 0xB373, fneg, FP32, FP32>;
355 def LPDFR_32 : UnaryRRE<"lpdfr", 0xB370, fabs, FP32, FP32>;
381 def FIEBR : BinaryRRFe<"fiebr", 0xB357, FP32, FP32>;
388 def : Pat<(any_frint FP32:$src), (FIEBR 0, FP32:$src)>;
396 def FIEBRA : TernaryRRFe<"fiebra", 0xB357, FP32, FP32>;
449 def SEBR : BinaryRRE<"sebr", 0xB30B, any_fsub, FP32, FP32>;
522 def DEBR : BinaryRRE<"debr", 0xB30D, any_fdiv, FP32, FP32>;
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H A DSystemZInstrDFP.td35 def LEDTR : TernaryRRFe<"ledtr", 0xB3D5, FP32, FP64>;
41 def LDETR : BinaryRRFd<"ldetr", 0xB3D4, FP64, FP32>;
235 def TDCET : TestRXE<"tdcet", 0xED50, null_frag, FP32>;
242 def TDGET : TestRXE<"tdget", 0xED51, null_frag, FP32>;
H A DSystemZRegisterInfo.td243 defm FP32 : SystemZRegClass<"FP32", [f32], 32, (sequence "F%uS", 0, 15)>;
H A DSystemZInstrVector.td1619 defm : ScalarToVectorFP<VREPF, v4f32, FP32, subreg_h32>;
/openbsd/gnu/llvm/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegisterInfo.td30 def FP32 : WebAssemblyReg<"%FP32">;
62 def I32 : WebAssemblyRegClass<[i32], 32, (add FP32, SP32, I32_0)>;
H A DWebAssemblyRegisterInfo.cpp47 for (auto Reg : {WebAssembly::SP32, WebAssembly::SP64, WebAssembly::FP32, in getReservedRegs()
148 /* hasFP */ {WebAssembly::FP32, WebAssembly::FP64}}; in getFrameRegister()
H A DWebAssemblyFrameLowering.cpp182 : WebAssembly::FP32; in getFPReg()
/openbsd/gnu/llvm/clang/lib/Basic/Targets/
H A DMips.h58 enum FPModeEnum { FPXX, FP32, FP64 } FPMode; enumerator
338 FPMode = FP32; in handleTargetFeatures()
H A DMips.cpp140 case FP32: in getTargetDefines()
/openbsd/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64.td441 "true", "Enable Matrix Multiply FP32 Extension (FEAT_F32MM)", [FeatureSVE]>;
/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DVOP3PInstructions.td572 // FP32 denorm mode is respected, rounding mode is not. Exceptions are not supported.
/openbsd/gnu/llvm/llvm/include/llvm/IR/
H A DIntrinsicsAArch64.td2563 // SVE ACLE: 7.4/5. FP64/FP32 matrix multiply extensions