| /openbsd/gnu/llvm/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 23 #ifndef INSTRUCTION
24 #define INSTRUCTION(N,A,R,I)
27 // DAG_INSTRUCTION is treated like an INSTRUCTION if the DAG node isn't used.
29 #define DAG_INSTRUCTION(N,A,R,I,D) INSTRUCTION(N,A,R,I)
34 #define FUNCTION(N,A,R,I) INSTRUCTION(N,A,R,I)
103 #undef INSTRUCTION
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| /openbsd/gnu/llvm/llvm/docs/AMDGPU/ |
| H A D | AMDGPUAsmGFX1011.rst | 41 **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS**
51 …**INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS…
61 **INSTRUCTION** **DST** **SRC0** **SRC1**
71 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** …
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| H A D | AMDGPUAsmGFX906.rst | 41 **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS**
54 **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS**
64 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIF…
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| H A D | AMDGPUAsmGFX908.rst | 41 **INSTRUCTION** **SRC0** **SRC1** **SRC2** **MODIFIERS**
51 …**INSTRUCTION** **SRC0** **SRC1** **SRC2** **SRC3** **…
61 **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS**
83 …**INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIE…
97 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** …
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| H A D | AMDGPUAsmGFX1013.rst | 41 **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS**
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| H A D | AMDGPUAsmGFX904.rst | 41 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MO…
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| H A D | AMDGPUAsmGFX900.rst | 41 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MO…
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| H A D | AMDGPUAsmGFX7.rst | 39 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** …
193 …**INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIER…
427 **INSTRUCTION** **DST** **SRC0** **SRC1**
448 **INSTRUCTION** **DST** **SRC**
504 **INSTRUCTION** **DST** **SRC0** **SRC1**
555 **INSTRUCTION** **SRC0** **SRC1**
580 **INSTRUCTION** **DST** **SRC0** **SRC1**
608 **INSTRUCTION** **SRC**
642 **INSTRUCTION** **DST** **SRC0** **SRC1**
653 **INSTRUCTION** **DST** **SRC**
[all …]
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| H A D | AMDGPUAsmGFX10.rst | 39 …**INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **…
562 **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
1103 **INSTRUCTION** **DST** **SRC**
1176 **INSTRUCTION** **DST** **SRC0** **SRC1**
1235 **INSTRUCTION** **SRC0** **SRC1**
1261 **INSTRUCTION** **DST** **SRC0** **SRC1**
1296 **INSTRUCTION** **SRC**
1341 **INSTRUCTION** **DST** **SRC0** **SRC1**
1352 **INSTRUCTION** **DST** **SRC**
1932 … **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
[all …]
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| H A D | AMDGPUAsmGFX1030.rst | 41 …**INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **…
538 **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
991 **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS**
1013 **INSTRUCTION** **DST** **SRC**
1086 **INSTRUCTION** **DST** **SRC0** **SRC1**
1145 **INSTRUCTION** **SRC0** **SRC1**
1171 **INSTRUCTION** **DST** **SRC0** **SRC1**
1206 **INSTRUCTION** **SRC**
1250 **INSTRUCTION** **DST** **SRC0** **SRC1**
1261 **INSTRUCTION** **DST** **SRC**
[all …]
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| H A D | AMDGPUAsmGFX8.rst | 39 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** …
200 …**INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIER…
248 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFI…
468 **INSTRUCTION** **DST** **SRC**
525 **INSTRUCTION** **DST** **SRC0** **SRC1**
577 **INSTRUCTION** **SRC0** **SRC1**
605 **INSTRUCTION** **DST** **SRC0** **SRC1**
633 **INSTRUCTION** **SRC**
671 **INSTRUCTION** **DST** **SRC0** **SRC1**
682 **INSTRUCTION** **DST** **SRC** **MODIFIERS**
[all …]
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| H A D | AMDGPUAsmGFX9.rst | 39 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** …
336 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
627 **INSTRUCTION** **DST** **SRC**
689 **INSTRUCTION** **DST** **SRC0** **SRC1**
750 **INSTRUCTION** **SRC0** **SRC1**
778 **INSTRUCTION** **DST** **SRC0** **SRC1**
807 **INSTRUCTION** **SRC**
846 **INSTRUCTION** **DST** **SRC0** **SRC1**
857 **INSTRUCTION** **DST** **SRC** **MODIFIERS**
1665 … **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
[all …]
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| H A D | AMDGPUAsmGFX11.rst | 469 **INSTRUCTION** **DST** **SRC** **MODIFIERS**
782 **INSTRUCTION** **DST** **SRC**
873 **INSTRUCTION** **DST** **SRC0** **SRC1**
937 **INSTRUCTION** **SRC0** **SRC1**
963 **INSTRUCTION** **DST** **SRC0** **SRC1**
998 **INSTRUCTION** **SRC**
1059 **INSTRUCTION** **DST** **SRC**
1156 **INSTRUCTION** **DST** **SRC** **MODIFIERS**
1231 **INSTRUCTION** **DST** **SRC** **MODIFIERS**
2682 **INSTRUCTION** **DST** **SRC0** **SRC1**
[all …]
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| H A D | AMDGPUAsmGFX90a.rst | 39 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** …
305 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFI…
338 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MO…
538 **INSTRUCTION** **DST** **SRC**
600 **INSTRUCTION** **DST** **SRC0** **SRC1**
661 **INSTRUCTION** **SRC0** **SRC1**
689 **INSTRUCTION** **DST** **SRC0** **SRC1**
718 **INSTRUCTION** **SRC**
757 **INSTRUCTION** **DST** **SRC** **MODIFIERS**
969 …**INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **M…
[all …]
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| H A D | AMDGPUAsmGFX940.rst | 39 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** …
175 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** …
323 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODI…
520 **INSTRUCTION** **DST** **SRC**
582 **INSTRUCTION** **DST** **SRC0** **SRC1**
643 **INSTRUCTION** **SRC0** **SRC1**
671 **INSTRUCTION** **DST** **SRC0** **SRC1**
700 **INSTRUCTION** **SRC**
739 **INSTRUCTION** **DST** **SRC** **MODIFIERS**
965 …**INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **M…
[all …]
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| /openbsd/gnu/llvm/llvm/lib/IR/ |
| H A D | FPEnv.cpp | 100 #define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC) \ in getConstrainedIntrinsicID() macro
116 #define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC) in getConstrainedIntrinsicID() macro
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| H A D | IntrinsicInst.cpp | 358 #define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC) \ in isUnaryOp() macro
369 #define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC) \ in isTernaryOp() macro
378 #define INSTRUCTION(NAME, NARGS, ROUND_MODE, INTRINSIC) \ in classof() macro
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| H A D | IRBuilder.cpp | 1052 #define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC) \ in CreateConstrainedFPCast() macro
1111 #define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC) \ in CreateConstrainedFPCall() macro
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| H A D | Function.cpp | 460 #define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC) \ in isConstrainedFPIntrinsic() macro
464 #undef INSTRUCTION in isConstrainedFPIntrinsic()
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| /openbsd/gnu/llvm/llvm/lib/Target/Mips/ |
| H A D | MipsInstrFormats.td | 12 // CPU INSTRUCTION FORMATS
666 // FLOATING POINT INSTRUCTION FORMATS
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| H A D | Mips16InstrFormats.td | 12 // CPU INSTRUCTION FORMATS
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| /openbsd/gnu/llvm/llvm/lib/Target/M68k/ |
| H A D | M68kInstrFormats.td | 474 // M68k INSTRUCTION. Most instructions specify the location of an operand by
507 // M68k PSEUDO INSTRUCTION
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| /openbsd/gnu/llvm/llvm/lib/Transforms/Utils/ |
| H A D | CloneFunction.cpp | 379 #define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC) \ in hasRoundingModeOperand() macro
382 #define FUNCTION INSTRUCTION in hasRoundingModeOperand()
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| /openbsd/gnu/usr.bin/gcc/gcc/java/ |
| H A D | expr.c | 2751 #define PRE_SPECIAL(OPERAND_TYPE, INSTRUCTION) \ argument
2752 PRE_SPECIAL_##INSTRUCTION(OPERAND_TYPE)
3206 #define SPECIAL(OPERAND_TYPE, INSTRUCTION) \ argument
3207 SPECIAL_##INSTRUCTION(OPERAND_TYPE)
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| /openbsd/gnu/gcc/gcc/config/i386/ |
| H A D | ppro.md | 48 ;; INSTRUCTION POOL __________|_______/
|