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Searched refs:LB_MEMORY_CTRL (Results 1 – 10 of 10) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/display/dc/dce/
H A Ddce_transform.h93 SRI(LB_MEMORY_CTRL, LB, id), \
247 XFM_SF(LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mask_sh), \
248 XFM_SF(LB_MEMORY_CTRL, LB_MEMORY_SIZE, mask_sh), \
602 uint32_t LB_MEMORY_CTRL; member
H A Ddce_transform.c418 REG_SET_2(LB_MEMORY_CTRL, 0, in dce_transform_set_scaler()
/openbsd/sys/dev/pci/drm/amd/display/dc/dcn10/
H A Ddcn10_dpp_dscl.c210 REG_SET_2(LB_MEMORY_CTRL, 0, in dpp1_dscl_set_lb()
H A Ddcn10_dpp.h60 SRI(LB_MEMORY_CTRL, DSCL, id), \
1112 uint32_t LB_MEMORY_CTRL; \
/openbsd/sys/dev/pci/drm/amd/display/dc/dcn30/
H A Ddcn30_dpp.h103 SRI(LB_MEMORY_CTRL, DSCL, id), \
/openbsd/sys/dev/pci/drm/radeon/
H A Dcikd.h864 #define LB_MEMORY_CTRL 0x6b04 macro
H A Dcik.c8836 WREG32(LB_MEMORY_CTRL + radeon_crtc->crtc_offset, in dce8_line_buffer_adjust()
/openbsd/sys/dev/pci/drm/amd/display/dc/dcn32/
H A Ddcn32_resource.h495 SRI_ARR(LB_MEMORY_CTRL, DSCL, id), SRI_ARR(DSCL_AUTOCAL, DSCL, id), \
/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Ddce_v10_0.c626 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg); in dce_v10_0_line_buffer_adjust()
H A Ddce_v11_0.c658 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg); in dce_v11_0_line_buffer_adjust()