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Searched refs:MAX_PIPES (Results 1 – 25 of 49) sorted by relevance

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/openbsd/sys/dev/pci/drm/amd/display/dc/inc/
H A Dcore_types.h208 struct mem_input *mis[MAX_PIPES];
209 struct hubp *hubps[MAX_PIPES];
212 struct dpp *dpps[MAX_PIPES];
219 struct dce_aux *engines[MAX_PIPES];
220 struct dce_i2c_hw *hw_i2cs[MAX_PIPES];
221 struct dce_i2c_sw *sw_i2cs[MAX_PIPES];
253 struct dc_3dlut *mpc_lut[MAX_PIPES];
286 struct abm *multiple_abms[MAX_PIPES];
426 struct pipe_ctx pipe_ctx[MAX_PIPES];
428 bool is_audio_acquired[MAX_PIPES];
[all …]
/openbsd/sys/dev/pci/drm/amd/display/dc/core/
H A Ddc_link_enc_cfg.c113 for (i = 0; i < MAX_PIPES; i++) { in remove_link_enc_assignment()
249 for (i = 0; i < MAX_PIPES; i++) { in get_link_enc_used_by_link()
263 for (i = 0; i < MAX_PIPES; i++) { in clear_enc_assignments()
313 for (i = 0; i < MAX_PIPES; i++) in link_enc_cfg_link_encs_assign()
409 for (i = 0; i < MAX_PIPES; i++) { in link_enc_cfg_link_encs_assign()
415 for (i = 0; i < MAX_PIPES; i++) { in link_enc_cfg_link_encs_assign()
428 for (i = 0; i < MAX_PIPES; i++) { in link_enc_cfg_link_encs_assign()
479 for (i = 0; i < MAX_PIPES; i++) { in link_enc_cfg_get_stream_using_link_enc()
518 for (i = 0; i < MAX_PIPES; i++) { in link_enc_cfg_get_link_enc_used_by_link()
540 for (i = 0; i < MAX_PIPES; i++) { in link_enc_cfg_get_next_avail_link_enc()
[all …]
H A Ddc_stream.c264 for (i = 0; i < MAX_PIPES; i++) { in program_cursor_attributes()
409 for (i = 0; i < MAX_PIPES; i++) { in program_cursor_position()
582 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_vblank_counter()
610 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_send_dp_sdp()
641 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_scanoutpos()
668 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_dmdata_status_done()
674 if (i == MAX_PIPES) in dc_stream_dmdata_status_done()
696 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_set_dynamic_metadata()
702 if (i == MAX_PIPES) in dc_stream_set_dynamic_metadata()
736 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_pipe_ctx()
H A Damdgpu_dc.c416 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_adjust_vmin_vmax()
451 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_last_used_drr_vtotal()
481 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_crtc_position()
542 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_forward_crc_window()
549 if (i == MAX_PIPES) in dc_stream_forward_crc_window()
659 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_crc()
665 if (i == MAX_PIPES) in dc_stream_get_crc()
683 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_set_dyn_expansion()
705 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_set_dither_option()
5190 if (i == MAX_PIPES) { in dc_notify_vsync_int_state()
[all …]
H A Ddc_debug.c312 int h_pos[MAX_PIPES] = {0}, v_pos[MAX_PIPES] = {0}; in context_timing_trace()
/openbsd/sys/dev/pci/drm/amd/display/dc/dcn20/
H A Ddcn20_dccg.h132 type OTG_ADD_PIXEL[MAX_PIPES];\
133 type OTG_DROP_PIXEL[MAX_PIPES];
168 type DTBCLK_DTO_ENABLE[MAX_PIPES];\
169 type DTBCLKDTO_ENABLE_STATUS[MAX_PIPES];\
170 type PIPE_DTO_SRC_SEL[MAX_PIPES];\
171 type DTBCLK_DTO_DIV[MAX_PIPES];\
264 uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES];
271 uint32_t DTBCLK_DTO_MODULO[MAX_PIPES];
272 uint32_t DTBCLK_DTO_PHASE[MAX_PIPES];
/openbsd/sys/dev/pci/drm/amd/display/dc/inc/hw/
H A Dopp.h200 int dpp[MAX_PIPES];
201 int mpcc[MAX_PIPES];
209 bool mpcc_disconnect_pending[MAX_PIPES];
H A Ddccg.h69 int pipe_dppclk_khz[MAX_PIPES];
71 bool dpp_clock_gated[MAX_PIPES];
H A Dhw_shared.h45 #define MAX_PIPES 6 macro
H A Dclk_mgr_internal.h338 unsigned int cur_phyclk_req_table[MAX_PIPES * 2];
/openbsd/sys/dev/pci/drm/amd/display/dc/dce/
H A Ddce_clock_source.h228 uint32_t PHASE[MAX_PIPES];
229 uint32_t MODULO[MAX_PIPES];
230 uint32_t PIXEL_RATE_CNTL[MAX_PIPES];
H A Ddmub_replay.c34 #define MAX_PIPES 6 macro
150 for (i = 0; i < MAX_PIPES; i++) { in dmub_replay_copy_settings()
H A Ddmub_psr.c34 #define MAX_PIPES 6 macro
307 for (i = 0; i < MAX_PIPES; i++) { in dmub_psr_copy_settings()
/openbsd/sys/dev/pci/drm/amd/display/dc/link/
H A Dlink_dpms.h42 struct pipe_ctx *pipes[MAX_PIPES]);
H A Dlink_resource.c40 for (i = 0; i < MAX_PIPES; i++) { in link_get_cur_link_res()
/openbsd/sys/dev/pci/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_mst_types.c905 bool bpp_increased[MAX_PIPES]; in increase_dsc_bpp()
906 int initial_slack[MAX_PIPES]; in increase_dsc_bpp()
1008 bool tried[MAX_PIPES]; in try_disable_dsc()
1009 int kbps_increase[MAX_PIPES]; in try_disable_dsc()
1080 struct dsc_mst_fairness_params params[MAX_PIPES]; in compute_mst_dsc_configs_for_link()
1212 struct amdgpu_dm_connector *stream_on_link[MAX_PIPES]; in is_dsc_need_re_compute()
1226 for (i = 0; i < MAX_PIPES; i++) in is_dsc_need_re_compute()
1312 bool computed_streams[MAX_PIPES]; in compute_mst_dsc_configs_for_state()
1376 bool computed_streams[MAX_PIPES]; in pre_compute_mst_dsc_configs_for_state()
H A Damdgpu_dm_debugfs.c1465 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_clock_en_read()
1568 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_clock_en_write()
1655 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_slice_width_read()
1756 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_slice_width_write()
1843 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_slice_height_read()
1944 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_slice_height_write()
2027 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_bits_per_pixel_read()
2125 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_bits_per_pixel_write()
2206 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_pic_width_read()
2264 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_pic_height_read()
[all …]
/openbsd/sys/dev/pci/drm/amd/display/dc/dcn314/
H A Ddcn314_hwseq.c185 int opp_inst[MAX_PIPES] = {0}; in dcn314_update_odm()
397 bool otg_disabled[MAX_PIPES] = {false}; in dcn314_resync_fifo_dccg_dio()
454 for (i = 0; i < MAX_PIPES; i++) { in apply_symclk_on_tx_off_wa()
/openbsd/sys/dev/pci/drm/amd/display/dc/link/accessories/
H A Dlink_dp_cts.c83 struct pipe_ctx *pipes[MAX_PIPES]; in dp_retrain_link_dp_test()
674 for (i = 0; i < MAX_PIPES; i++) { in dp_set_test_pattern()
969 for (i = 0; i < MAX_PIPES; i++) { in dp_set_preferred_link_settings()
980 if (i == MAX_PIPES) in dp_set_preferred_link_settings()
/openbsd/sys/dev/pci/drm/amd/display/dc/
H A Ddc_stream.h171 struct mall_stream_config mall_stream_config[MAX_PIPES];
172 bool is_phantom_plane[MAX_PIPES];
/openbsd/sys/dev/pci/drm/amd/display/dc/link/protocols/
H A Dlink_edp_panel_control.c500 for (i = 0; i < MAX_PIPES; i++) { in get_pipe_from_link()
735 for (i = 0; i < MAX_PIPES; i++) { in edp_setup_psr()
955 for (i = 0; i < MAX_PIPES; i++) { in edp_setup_replay()
1041 for (i = 0; i < MAX_PIPES; i++) { in get_abm_from_stream_res()
H A Dlink_dp_dpia_bw.c169 for (i = 0; i < MAX_PIPES * 2; ++i) { in get_lowest_dpia_index()
199 for (uint8_t i = 0; i < (MAX_PIPES * 2) - 1; ++i) { in get_host_router_total_dp_tunnel_bw()
/openbsd/sys/dev/pci/drm/amd/display/dc/dcn32/
H A Ddcn32_resource_helpers.c287 uint8_t pipe_plane_count, stream_segments, plane_segments, pipe_segments[MAX_PIPES] = {0}; in dcn32_determine_det_override()
288 uint8_t pipe_counted[MAX_PIPES] = {0}; in dcn32_determine_det_override()
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/
H A Ddce110_clk_mgr.c134 for (k = 0; k < MAX_PIPES; k++) in dce110_fill_display_configs()
/openbsd/sys/dev/pci/drm/amd/display/dc/irq/dce110/
H A Dirq_service_dce110.c216 if (pipe_offset >= MAX_PIPES) in dce110_vblank_set()

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