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Searched refs:MO1 (Results 1 – 22 of 22) sorted by relevance

/openbsd/gnu/llvm/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp113 printRegName(O, MO1.getReg()); in printInst()
135 printRegName(O, MO1.getReg()); in printInst()
370 if (MO1.isExpr()) { in printThumbLdrLabelOperand()
403 printRegName(O, MO1.getReg()); in printSORegRegOperand()
422 printRegName(O, MO1.getReg()); in printSORegImmOperand()
441 printRegName(O, MO1.getReg()); in printAM2PreOrOffsetIndexOp()
468 printRegName(O, MO1.getReg()); in printAddrModeTBB()
480 printRegName(O, MO1.getReg()); in printAddrModeTBH()
512 if (!MO1.getReg()) { in printAddrMode2OffsetOperand()
582 if (MO1.getReg()) { in printAddrMode3OffsetOperand()
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H A DARMMCCodeEmitter.cpp599 int32_t SImm = MO1.getImm(); in EncodeAddrModeOpValues()
986 if (MO1.isImm()) { in getAddrModeImm12OpValue()
988 } else if (MO1.isExpr()) { in getAddrModeImm12OpValue()
1188 unsigned Imm8 = MO1.getImm(); in getT2AddrModeImm0_1020s4OpValue()
1291 unsigned Imm = MO1.getImm(); in getAddrMode2OffsetOpValue()
1313 bool isAdd = MO1.getImm() != 0; in getPostIdxRegOpValue()
1327 unsigned Imm = MO1.getImm(); in getAddrMode3OffsetOpValue()
1365 bool isImm = MO1.getReg() == 0; in getAddrMode3OpValue()
1386 return MO1.getImm() & 0xff; in getAddrModeThumbSPOpValue()
1400 unsigned Imm5 = MO1.getImm(); in getAddrModeISOpValue()
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H A DARMMCTargetDesc.cpp448 const MCOperand &MO1 = Inst.getOperand(MemOpIndex); in evaluateMemOpAddrForAddrMode_i12() local
450 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm()) in evaluateMemOpAddrForAddrMode_i12()
466 const MCOperand &MO1 = Inst.getOperand(MemOpIndex); in evaluateMemOpAddrForAddrMode3() local
469 if (!MO1.isReg() || MO1.getReg() != ARM::PC || MO2.getReg() || !MO3.isImm()) in evaluateMemOpAddrForAddrMode3()
486 const MCOperand &MO1 = Inst.getOperand(MemOpIndex); in evaluateMemOpAddrForAddrMode5() local
488 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm()) in evaluateMemOpAddrForAddrMode5()
505 const MCOperand &MO1 = Inst.getOperand(MemOpIndex); in evaluateMemOpAddrForAddrMode5FP16() local
507 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm()) in evaluateMemOpAddrForAddrMode5FP16()
527 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm()) in evaluateMemOpAddrForAddrModeT2_i8s4()
544 if (!MO1.isImm()) in evaluateMemOpAddrForAddrModeT2_pc()
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/openbsd/gnu/llvm/llvm/lib/Target/X86/
H A DX86OptimizeLEAs.cpp72 static bool isSimilarDispOp(const MachineOperand &MO1,
203 return MO1.isIdenticalTo(MO2) && (!MO1.isReg() || !MO1.getReg().isPhysical()); in isIdenticalOp()
215 assert(isValidDispOp(MO1) && isValidDispOp(MO2) && in isSimilarDispOp()
217 return (MO1.isImm() && MO2.isImm()) || in isSimilarDispOp()
218 (MO1.isCPI() && MO2.isCPI() && MO1.getIndex() == MO2.getIndex()) || in isSimilarDispOp()
219 (MO1.isJTI() && MO2.isJTI() && MO1.getIndex() == MO2.getIndex()) || in isSimilarDispOp()
220 (MO1.isSymbol() && MO2.isSymbol() && in isSimilarDispOp()
222 (MO1.isGlobal() && MO2.isGlobal() && in isSimilarDispOp()
223 MO1.getGlobal() == MO2.getGlobal()) || in isSimilarDispOp()
226 (MO1.isMCSymbol() && MO2.isMCSymbol() && in isSimilarDispOp()
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H A DX86RegisterInfo.cpp966 MachineOperand &MO1 = MI->getOperand(1); in getTileShape() local
968 ShapeT Shape(&MO1, &MO2, MRI); in getTileShape()
H A DX86FloatingPoint.cpp1527 const MachineOperand &MO1 = MI.getOperand(1); in handleSpecialFP() local
1529 bool KillsSrc = MI.killsRegister(MO1.getReg()); in handleSpecialFP()
1533 unsigned SrcFP = getFPReg(MO1); in handleSpecialFP()
H A DX86InstrInfo.cpp7001 MachineOperand &MO1 = DataMI->getOperand(1); in unfoldMemoryOperand() local
7002 if (MO1.isImm() && MO1.getImm() == 0) { in unfoldMemoryOperand()
7015 MO1.ChangeToRegister(MO0.getReg(), false); in unfoldMemoryOperand()
/openbsd/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64ExpandPseudoInsts.cpp1155 const MachineOperand &MO1 = MI.getOperand(1); in expandMI() local
1156 unsigned Flags = MO1.getTargetFlags(); in expandMI()
1163 if (MO1.isGlobal()) { in expandMI()
1165 } else if (MO1.isSymbol()) { in expandMI()
1168 assert(MO1.isCPI() && in expandMI()
1170 MIB.addConstantPoolIndex(MO1.getIndex(), MO1.getOffset(), Flags); in expandMI()
1195 if (MO1.isGlobal()) { in expandMI()
1199 } else if (MO1.isSymbol()) { in expandMI()
1205 assert(MO1.isCPI() && in expandMI()
1207 MIB1.addConstantPoolIndex(MO1.getIndex(), MO1.getOffset(), in expandMI()
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/openbsd/gnu/llvm/llvm/lib/Target/MSP430/MCTargetDesc/
H A DMSP430MCCodeEmitter.cpp123 const MCOperand &MO1 = MI.getOperand(Op); in getMemOpValue() local
124 assert(MO1.isReg() && "Register operand expected"); in getMemOpValue()
125 unsigned Reg = Ctx.getRegisterInfo()->getEncodingValue(MO1.getReg()); in getMemOpValue()
/openbsd/gnu/llvm/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp202 auto MO1 = *L1->memoperands().begin(); in getHazardType() local
203 auto BaseVal1 = MO1->getValue(); in getHazardType()
204 auto BasePseudoVal1 = MO1->getPseudoValue(); in getHazardType()
H A DARMAsmPrinter.cpp978 const MachineOperand &MO1 = MI->getOperand(1); in emitJumpTableAddrs() local
979 unsigned JTI = MO1.getIndex(); in emitJumpTableAddrs()
1024 const MachineOperand &MO1 = MI->getOperand(1); in emitJumpTableInsts() local
1025 unsigned JTI = MO1.getIndex(); in emitJumpTableInsts()
1054 const MachineOperand &MO1 = MI->getOperand(1); in emitJumpTableTBInst() local
1055 unsigned JTI = MO1.getIndex(); in emitJumpTableTBInst()
H A DARMExpandPseudoInsts.cpp2555 const MachineOperand &MO1 = MI.getOperand(1); in ExpandMI() local
2556 auto Flags = MO1.getTargetFlags(); in ExpandMI()
2557 const GlobalValue *GV = MO1.getGlobal(); in ExpandMI()
2616 const MachineOperand &MO1 = MI.getOperand(1); in ExpandMI() local
2617 const GlobalValue *GV = MO1.getGlobal(); in ExpandMI()
2618 unsigned TF = MO1.getTargetFlags(); in ExpandMI()
2629 .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF) in ExpandMI()
2634 .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF) in ExpandMI()
H A DARMBaseInstrInfo.cpp1876 const MachineOperand &MO1 = MI1.getOperand(1); in produceSameValue() local
1877 if (MO0.getOffset() != MO1.getOffset()) in produceSameValue()
1885 return MO0.getGlobal() == MO1.getGlobal(); in produceSameValue()
1890 int CPI1 = MO1.getIndex(); in produceSameValue()
1929 const MachineOperand &MO1 = MI1.getOperand(i); in produceSameValue() local
1930 if (!MO0.isIdenticalTo(MO1)) in produceSameValue()
/openbsd/gnu/llvm/llvm/lib/CodeGen/
H A DRegAllocFast.cpp1242 const MachineOperand &MO1 = MI.getOperand(I1); in allocateInstruction() local
1244 Register Reg1 = MO1.getReg(); in allocateInstruction()
1263 bool Livethrough1 = MO1.isEarlyClobber() || MO1.isTied() || in allocateInstruction()
1264 (MO1.getSubReg() == 0 && !MO1.isUndef()); in allocateInstruction()
H A DMachineVerifier.cpp2799 const MachineOperand &MO1 = Phi.getOperand(I + 1); in checkPHIOps() local
2800 if (!MO1.isMBB()) { in checkPHIOps()
2801 report("Expected PHI operand to be a basic block", &MO1, I + 1); in checkPHIOps()
2805 const MachineBasicBlock &Pre = *MO1.getMBB(); in checkPHIOps()
2807 report("PHI input is not a predecessor block", &MO1, I + 1); in checkPHIOps()
/openbsd/gnu/llvm/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCCodeEmitter.cpp280 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); in getAddSubImmOpValue() local
281 assert(AArch64_AM::getShiftType(MO1.getImm()) == AArch64_AM::LSL && in getAddSubImmOpValue()
283 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm()); in getAddSubImmOpValue()
H A DAArch64InstPrinter.cpp1407 const MCOperand MO1 = MI->getOperand(OpNum + 1); in printAMIndexedWB() local
1410 if (MO1.isImm()) { in printAMIndexedWB()
1411 O << ", " << markup("<imm:") << "#" << formatImm(MO1.getImm() * Scale) in printAMIndexedWB()
1414 assert(MO1.isExpr() && "Unexpected operand type!"); in printAMIndexedWB()
1416 MO1.getExpr()->print(O, &MAI); in printAMIndexedWB()
/openbsd/gnu/llvm/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp1233 static MCInst makeCombineInst(int opCode, MCOperand &Rdd, MCOperand &MO1, in makeCombineInst() argument
1238 TmpInst.addOperand(MO1); in makeCombineInst()
1595 MCOperand &MO1 = Inst.getOperand(1); in processInstruction() local
1603 Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, MO1, MO2); in processInstruction()
1610 MCOperand &MO1 = Inst.getOperand(1); in processInstruction() local
1612 if (MO1.getExpr()->evaluateAsAbsolute(Value)) { in processInstruction()
1618 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, MO1, MO2); in processInstruction()
/openbsd/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonAsmPrinter.cpp464 MCOperand &MO1 = MappedInst.getOperand(1); in HexagonProcessInstruction() local
465 unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
466 unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
/openbsd/gnu/llvm/llvm/docs/
H A DWritingAnLLVMBackend.rst1937 const MachineOperand &MO1 = MI.getOperand(CurOp++);
1939 if (MO1.isImmediate())
1940 emitConstant(MO1.getImm(), Size);
1946 if (MO1.isGlobalAddress()) {
1948 bool isLazy = gvNeedsLazyPtr(MO1.getGlobal());
1949 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
1951 } else if (MO1.isExternalSymbol())
1953 else if (MO1.isConstantPoolIndex())
1954 emitConstPoolAddress(MO1.getIndex(), rt);
1955 else if (MO1.isJumpTableIndex())
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/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp463 auto MO1 = *MI1.memoperands_begin(); in memOpsHaveSameBasePtr() local
465 if (MO1->getAddrSpace() != MO2->getAddrSpace()) in memOpsHaveSameBasePtr()
468 auto Base1 = MO1->getValue(); in memOpsHaveSameBasePtr()
/openbsd/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp1299 MachineOperand &MO1 = MI.getOperand(1); in narrowScalar() local
1300 auto TruncMIB = MIRBuilder.buildTrunc(NarrowTy, MO1); in narrowScalar()
1301 MO1.setReg(TruncMIB.getReg(0)); in narrowScalar()