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Searched refs:REGVAL (Results 1 – 25 of 26) sorted by relevance

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/openbsd/sys/arch/loongson/dev/
H A Dbonito.c256 REGVAL(BONITO_MEM_WIN_BASE_H), REGVAL(BONITO_MEM_WIN_BASE_L), in bonito_attach()
257 REGVAL(BONITO_MEM_WIN_MASK_H), REGVAL(BONITO_MEM_WIN_MASK_L)); in bonito_attach()
315 (void)REGVAL(BONITO_INTENCLR); in bonito_attach()
584 isr = REGVAL(BONITO_INTISR); in bonito_intr_2e()
593 isr = REGVAL(BONITO_INTISR); in bonito_intr_2e()
597 imr = REGVAL(BONITO_INTEN); in bonito_intr_2e()
642 imr = REGVAL(BONITO_INTEN); in bonito_intr_2f()
715 REGVAL(BONITO_INTISR), REGVAL(BONITO_INTEN), in bonito_intr_dispatch()
864 imr = REGVAL(BONITO_INTEN); in bonito_conf_read_internal()
915 imr = REGVAL(BONITO_INTEN); in bonito_conf_write()
[all …]
H A Dkb3310.c479 ykbec_chip_config = REGVAL(LOONGSON_CHIP_CONFIG0); in ykbec_suspend()
481 REGVAL(LOONGSON_CHIP_CONFIG0) = ykbec_chip_config & ~0x7; in ykbec_suspend()
482 (void)REGVAL(LOONGSON_CHIP_CONFIG0); in ykbec_suspend()
501 REGVAL(LOONGSON_CHIP_CONFIG0) = ykbec_chip_config; in ykbec_resume()
502 (void)REGVAL(LOONGSON_CHIP_CONFIG0); in ykbec_resume()
H A Dhtb.c278 return REGVAL(htb_cfg_space_addr(tag, offset)); in htb_conf_read()
284 REGVAL(htb_cfg_space_addr(tag, offset)) = data; in htb_conf_write()
/openbsd/sys/arch/alpha/pci/
H A Dmcpcia_dma.c198 REGVAL(MCPCIA_W0_BASE(ccp)) = 0;
199 REGVAL(MCPCIA_W1_BASE(ccp)) = 0;
200 REGVAL(MCPCIA_W2_BASE(ccp)) = 0;
201 REGVAL(MCPCIA_W3_BASE(ccp)) = 0;
202 REGVAL(MCPCIA_T0_BASE(ccp)) = 0;
203 REGVAL(MCPCIA_T1_BASE(ccp)) = 0;
212 REGVAL(MCPCIA_T0_BASE(ccp)) =
215 REGVAL(MCPCIA_W0_BASE(ccp)) =
227 REGVAL(MCPCIA_W1_BASE(ccp)) =
235 REGVAL(MCPCIA_T2_BASE(ccp)) =
[all …]
H A Dcia_pci.c142 REGVAL(CIA_CSR_CIA_ERR) = CIA_ERR_RCVD_MAS_ABT|CIA_ERR_RCVD_TAR_ABT;
150 old_cfg = REGVAL(CIA_CSR_CFG);
152 REGVAL(CIA_CSR_CFG) = old_cfg | 0x1;
186 REGVAL(CIA_CSR_CFG) = old_cfg;
193 errbits = REGVAL(CIA_CSR_CIA_ERR);
200 REGVAL(CIA_CSR_CIA_ERR) = errbits;
234 old_cfg = REGVAL(CIA_CSR_CFG);
236 REGVAL(CIA_CSR_CFG) = old_cfg | 0x1;
268 REGVAL(CIA_CSR_CFG) = old_cfg;
H A Dirongate_pci.c67 #define REGVAL(r) (*(volatile u_int32_t *)ALPHA_PHYS_TO_K0SEG(r)) macro
147 REGVAL(PCI_CONF_ADDR) = (CONFADDR_ENABLE | tag | (offset & 0xff)); in irongate_conf_read0()
149 data = REGVAL(PCI_CONF_DATA); in irongate_conf_read0()
150 REGVAL(PCI_CONF_ADDR) = 0; in irongate_conf_read0()
163 REGVAL(PCI_CONF_ADDR) = (CONFADDR_ENABLE | tag | (offset & 0xff)); in irongate_conf_write()
165 REGVAL(PCI_CONF_DATA) = data; in irongate_conf_write()
167 REGVAL(PCI_CONF_ADDR) = 0; in irongate_conf_write()
H A Dmcpcia.c185 ctl = REGVAL(MCPCIA_PCI_REV(ccp));
218 REGVAL(MCPCIA_CAP_ERR(ccp)) = 0xFFFFFFFF;
248 if (EISA_PRESENT(REGVAL(MCPCIA_PCI_REV(ccp)))) { in mcpcia_init()
288 REGVAL(MCPCIA_INT_MASK0(ccp)) = 0;
289 REGVAL(MCPCIA_INT_MASK1(ccp)) = 0;
290 REGVAL(MCPCIA_CAP_ERR(ccp)) = 0xFFFFFFFF;
298 ctl = REGVAL(MCPCIA_WHOAMI(ccp));
337 ctl = REGVAL(MCPCIA_INT_MASK0(ccp)); in mcpcia_config_cleanup()
339 REGVAL(MCPCIA_INT_MASK0(ccp)) = ctl; in mcpcia_config_cleanup()
343 ctl = REGVAL(MCPCIA_INT_MASK0(ccp)); in mcpcia_config_cleanup()
H A Dcia_dma.c176 REGVAL(CIA_PCI_W0BASE) = CIA_SGMAP_MAPPED_BASE |
180 REGVAL(CIA_PCI_W0MASK) = CIA_PCI_WnMASK_8M;
186 REGVAL(CIA_PCI_T0BASE) = tbase;
210 REGVAL(CIA_PCI_W2BASE) = CIA_PYXIS_BUG_BASE |
214 REGVAL(CIA_PCI_W2MASK) = CIA_PCI_WnMASK_2M;
221 REGVAL(CIA_PCI_T2BASE) = tbase;
464 REGVAL(CIA_PCI_TBIA) = CIA_PCI_TBIA_ALL; in cia_tlb_invalidate()
484 ctrl = REGVAL(CIA_CSR_CTRL); in cia_broken_pyxis_tlb_invalidate()
485 REGVAL(CIA_CSR_CTRL) = ctrl | CTRL_PCI_LOOP_EN; in cia_broken_pyxis_tlb_invalidate()
506 REGVAL(CIA_CSR_CTRL) = ctrl; in cia_broken_pyxis_tlb_invalidate()
H A Dapecs_pci.c135 old_haxr2 = REGVAL(EPIC_HAXR2);
137 REGVAL(EPIC_HAXR2) = old_haxr2 | 0x1;
152 REGVAL(EPIC_HAXR2) = old_haxr2;
184 old_haxr2 = REGVAL(EPIC_HAXR2);
186 REGVAL(EPIC_HAXR2) = old_haxr2 | 0x1;
203 REGVAL(EPIC_HAXR2) = old_haxr2;
H A Dcia.c172 ccp->cc_hae_mem = REGVAL(CIA_CSR_HAE_MEM);
173 ccp->cc_hae_io = REGVAL(CIA_CSR_HAE_IO);
174 ccp->cc_rev = REGVAL(CIA_CSR_REV) & REV_MASK;
193 ccp->cc_cnfg = REGVAL(CIA_CSR_CNFG);
232 ctrl = REGVAL(CIA_CSR_CTRL);
234 REGVAL(CIA_CSR_CTRL) = ctrl | CTRL_PCI_LOOP_EN;
353 ctrl = REGVAL(CIA_CSR_CTRL);
355 REGVAL(CIA_CSR_CTRL) = ctrl;
H A Dapecs.c134 (REGVAL(COMANCHE_ED) & COMANCHE_ED_PASS2) != 0;
136 (REGVAL(COMANCHE_GCR) & COMANCHE_GCR_WIDEMEM) != 0 ? 128 : 64;
138 (REGVAL(EPIC_DCSR) & EPIC_DCSR_PASS2) != 0;
140 acp->ac_haxr1 = REGVAL(EPIC_HAXR1);
141 acp->ac_haxr2 = REGVAL(EPIC_HAXR2);
H A Dapecs_dma.c89 REGVAL(EPIC_TBIA) = 0; \
157 REGVAL(EPIC_PCI_BASE_1) = 0;
171 REGVAL(EPIC_PCI_BASE_1) = APECS_SGMAP_MAPPED_BASE |
175 REGVAL(EPIC_PCI_MASK_1) = EPIC_PCI_MASK_8M;
181 REGVAL(EPIC_TBASE_1) = tbase;
H A Dlca_pci.c141 REGVAL(LCA_IOC_CONF) = 0x01;
170 REGVAL(LCA_IOC_CONF) = 0x00;
201 REGVAL(LCA_IOC_CONF) = 0x01;
222 REGVAL(LCA_IOC_CONF) = 0x00;
H A Dpci_kn300.c108 if (EISA_PRESENT(REGVAL(MCPCIA_PCI_REV(ccp)))) {
285 REGVAL(MCPCIA_INT_MASK0(ccp)) |= (1 << irq);
295 REGVAL(MCPCIA_INT_MASK0(ccp)) &= ~(1 << irq);
H A Dpci_kn20aa.c273 REGVAL(0x8780000000L + 0x40L) |= (1 << irq); /* XXX */
283 REGVAL(0x8780000000L + 0x40L) &= ~(1 << irq); /* XXX */
H A Dlcareg.h35 #define REGVAL(r) (*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r)) macro
H A Dciareg.h37 #define REGVAL(r) (*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r)) macro
H A Dapecsreg.h38 #define REGVAL(r) (*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r)) macro
/openbsd/sys/arch/loongson/loongson/
H A Dloongson3_intr.c90 REGVAL(LS3_IRT_INTENCLR(node)) = ~0u; in loongson3_intr_init()
355 REGVAL(LS3_IRT_INTENSET(0)) = in loongson3_splx()
379 isr = REGVAL(LS3_IRT_INTISR(0)); in loongson3_intr()
380 imr = REGVAL(LS3_IRT_INTEN(0)) & ~LS3_IRQ_HT_MASK; in loongson3_intr()
387 REGVAL(LS3_IRT_INTENCLR(0)) = isr; in loongson3_intr()
434 REGVAL(LS3_IRT_INTENSET(0)) = imr; in loongson3_intr()
460 REGVAL(LS3_IRT_INTENCLR(0)) = 1u << LS3_IRQ_HT1(0); in loongson3_ht_intr()
514 REGVAL(LS3_IRT_INTENSET(0)) = 1u << LS3_IRQ_HT1(0); in loongson3_ht_intr()
H A Dgdium_machdep.c267 REGVAL(BONITO_GPIODATA) |= 0x00000002; in gdium_powerdown()
268 REGVAL(BONITO_GPIOIE) &= ~0x00000002; in gdium_powerdown()
274 REGVAL(BONITO_GPIODATA) &= ~0x00000002; in gdium_reset()
275 REGVAL(BONITO_GPIOIE) &= ~0x00000002; in gdium_reset()
H A Dloongson2_machdep.c285 val = REGVAL(LOONGSON_CHIP_CONFIG0); in loongson2f_cpuspeed()
304 val = REGVAL(LOONGSON_CHIP_CONFIG0); in loongson2f_setperf()
306 REGVAL(LOONGSON_CHIP_CONFIG0) = val; in loongson2f_setperf()
307 (void)REGVAL(LOONGSON_CHIP_CONFIG0); in loongson2f_setperf()
H A Dyeeloong_machdep.c474 REGVAL(gpiobase + GPIOL_OUT_EN) = GPIO_ATOMIC_VALUE(13, 1); in fuloong_powerdown()
476 REGVAL(gpiobase + GPIOL_OUT_VAL) = GPIO_ATOMIC_VALUE(13, 0); in fuloong_powerdown()
482 REGVAL(BONITO_GPIODATA) &= ~0x00000001; in yeeloong_powerdown()
483 REGVAL(BONITO_GPIOIE) &= ~0x00000001; in yeeloong_powerdown()
H A Dgeneric2e_machdep.c331 REGVAL(LOONGSON_GENCFG) &= ~BONITO_GENCFG_CPUSELFRESET; in generic2e_reset()
332 REGVAL(LOONGSON_GENCFG) |= BONITO_GENCFG_CPUSELFRESET; in generic2e_reset()
/openbsd/sys/arch/loongson/include/
H A Dautoconf.h120 #define REGVAL(x) REGVAL32(x) macro
/openbsd/sys/arch/alpha/alpha/
H A Ddec_550.c277 REGVAL(PYXIS_GPO) = DEC_550_PYXIS_GPO_POWERDOWN; in dec_550_powerdown()

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