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Searched refs:RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK (Results 1 – 16 of 16) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Dgfx_v7_0.c3731 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; in gfx_v7_0_enable_gfx_cgpg()
3741 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; in gfx_v7_0_enable_gfx_cgpg()
H A Dgfx_v11_0.c4997 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; in gfx_v11_cntl_power_gating()
4999 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; in gfx_v11_cntl_power_gating()
H A Dgfx_v10_0.c7947 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; in gfx_v10_cntl_power_gating()
7949 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; in gfx_v10_cntl_power_gating()
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h7228 #define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L macro
H A Dgfx_7_2_sh_mask.h7839 #define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x1 macro
H A Dgfx_8_0_sh_mask.h8741 #define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x1 macro
H A Dgfx_8_1_sh_mask.h9293 #define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x1 macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h23062 #define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK … macro
H A Dgc_9_1_sh_mask.h24353 #define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK … macro
H A Dgc_9_2_1_sh_mask.h24406 #define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK … macro
H A Dgc_9_4_3_sh_mask.h26661 #define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK … macro
H A Dgc_9_4_2_sh_mask.h21856 #define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK … macro
H A Dgc_11_0_0_sh_mask.h34357 #define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK … macro
H A Dgc_10_1_0_sh_mask.h33515 #define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK … macro
H A Dgc_11_0_3_sh_mask.h37600 #define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK … macro
H A Dgc_10_3_0_sh_mask.h32536 #define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK … macro