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Searched refs:RREG32_SOC15_IP (Results 1 – 13 of 13) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Dsdma_v6_0.c387 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); in sdma_v6_0_gfx_stop()
390 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); in sdma_v6_0_gfx_stop()
453 f32_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); in sdma_v6_0_enable()
486 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); in sdma_v6_0_gfx_resume()
557 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL)); in sdma_v6_0_gfx_resume()
563 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE)); in sdma_v6_0_gfx_resume()
573 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); in sdma_v6_0_gfx_resume()
583 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); in sdma_v6_0_gfx_resume()
729 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE)); in sdma_v6_0_soft_reset()
732 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); in sdma_v6_0_soft_reset()
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H A Dsdma_v5_2.c374 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_2_gfx_stop()
377 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); in sdma_v5_2_gfx_stop()
507 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_2_gfx_resume()
528 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, in sdma_v5_2_gfx_resume()
557 doorbell = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); in sdma_v5_2_gfx_resume()
558 …doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSE… in sdma_v5_2_gfx_resume()
592 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); in sdma_v5_2_gfx_resume()
598 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); in sdma_v5_2_gfx_resume()
616 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); in sdma_v5_2_gfx_resume()
H A Dsdma_v5_0.c316 wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); in sdma_v5_0_ring_get_wptr()
318 wptr |= RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)); in sdma_v5_0_ring_get_wptr()
565 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_0_gfx_stop()
568 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); in sdma_v5_0_gfx_stop()
700 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_0_gfx_resume()
721 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, in sdma_v5_0_gfx_resume()
754 doorbell = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); in sdma_v5_0_gfx_resume()
755 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, in sdma_v5_0_gfx_resume()
812 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); in sdma_v5_0_gfx_resume()
H A Damdgpu_gmc.c674 RREG32_SOC15_IP(GC, reg) : in amdgpu_gmc_set_vm_fault_masks()
675 RREG32_SOC15_IP(MMHUB, reg); in amdgpu_gmc_set_vm_fault_masks()
H A Dgmc_v9_0.c498 tmp = RREG32_SOC15_IP(MMHUB, reg); in gmc_v9_0_vm_fault_interrupt_state()
500 tmp = RREG32_SOC15_IP(GC, reg); in gmc_v9_0_vm_fault_interrupt_state()
526 tmp = RREG32_SOC15_IP(MMHUB, reg); in gmc_v9_0_vm_fault_interrupt_state()
528 tmp = RREG32_SOC15_IP(GC, reg); in gmc_v9_0_vm_fault_interrupt_state()
H A Dsoc15_common.h70 #define RREG32_SOC15_IP(ip, reg) __RREG32_SOC15_RLC__(reg, 0, ip##_HWIP, 0) macro
H A Damdgpu_amdkfd_gfx_v10_3.c338 (*dump)[i++][1] = RREG32_SOC15_IP(GC, addr); \ in hqd_dump_v10_3()
H A Damdgpu_amdkfd_gfx_v10.c352 (*dump)[i++][1] = RREG32_SOC15_IP(GC, addr); \ in kgd_hqd_dump()
H A Dgfx_v11_0.c5740 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v11_0_set_gfx_eop_interrupt_state()
5748 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v11_0_set_gfx_eop_interrupt_state()
5797 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v11_0_set_compute_eop_interrupt_state()
5805 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v11_0_set_compute_eop_interrupt_state()
6023 tmp = RREG32_SOC15_IP(GC, target);
6033 tmp = RREG32_SOC15_IP(GC, target);
H A Damdgpu_amdkfd_gfx_v9.c971 reg_val = RREG32_SOC15_IP(GC, SOC15_REG_OFFSET(GC, inst, mmSPI_CSQ_WF_ACTIVE_COUNT_0) + in get_wave_count()
H A Dsoc15.c463 RREG32_SOC15_IP(GC, reg) : RREG32(reg); in soc15_program_register_sequence()
H A Dgfx_v10_0.c8787 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v10_0_set_gfx_eop_interrupt_state()
8793 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v10_0_set_gfx_eop_interrupt_state()
8840 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v10_0_set_compute_eop_interrupt_state()
8846 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v10_0_set_compute_eop_interrupt_state()
9065 tmp = RREG32_SOC15_IP(GC, target); in gfx_v10_0_kiq_set_interrupt_state()
9075 tmp = RREG32_SOC15_IP(GC, target); in gfx_v10_0_kiq_set_interrupt_state()
H A Dgfx_v9_0.c5763 mec_int_cntl = RREG32_SOC15_IP(GC,mec_int_cntl_reg); in gfx_v9_0_set_compute_eop_interrupt_state()
5769 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v9_0_set_compute_eop_interrupt_state()