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Searched refs:UVD_MPC_SET_MUXA0__VARA_4__SHIFT (Results 1 – 19 of 19) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h602 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT … macro
H A Duvd_3_1_sh_mask.h486 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 macro
H A Duvd_4_0_sh_mask.h505 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x00000018 macro
H A Duvd_4_2_sh_mask.h490 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 macro
H A Duvd_5_0_sh_mask.h522 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 macro
H A Duvd_6_0_sh_mask.h524 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1109 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT … macro
H A Dvcn_2_5_sh_mask.h2850 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT … macro
H A Dvcn_2_0_0_sh_mask.h2615 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT … macro
H A Dvcn_2_6_0_sh_mask.h2842 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT … macro
H A Dvcn_3_0_0_sh_mask.h3923 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT … macro
H A Dvcn_4_0_0_sh_mask.h4173 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT … macro
H A Dvcn_4_0_3_sh_mask.h4216 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT … macro
/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Dvcn_v4_0_3.c792 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); in vcn_v4_0_3_start_dpg_mode()
1118 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); in vcn_v4_0_3_start()
H A Dvcn_v1_0.c840 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); in vcn_v1_0_start_spg_mode()
1023 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0xFFFFFFFF, 0); in vcn_v1_0_start_dpg_mode()
H A Dvcn_v2_0.c847 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); in vcn_v2_0_start_dpg_mode()
980 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); in vcn_v2_0_start()
H A Dvcn_v4_0.c966 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); in vcn_v4_0_start_dpg_mode()
1105 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); in vcn_v4_0_start()
H A Dvcn_v2_5.c872 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); in vcn_v2_5_start_dpg_mode()
1026 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); in vcn_v2_5_start()
H A Dvcn_v3_0.c995 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); in vcn_v3_0_start_dpg_mode()
1159 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); in vcn_v3_0_start()