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Searched refs:UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK (Results 1 – 13 of 13) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h653 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK … macro
H A Duvd_3_1_sh_mask.h523 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x1ffffff macro
H A Duvd_4_0_sh_mask.h750 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x01ffffffL macro
H A Duvd_4_2_sh_mask.h527 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x1ffffff macro
H A Duvd_5_0_sh_mask.h559 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x1ffffff macro
H A Duvd_6_0_sh_mask.h561 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x1ffffff macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1173 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK … macro
H A Dvcn_2_5_sh_mask.h2683 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK … macro
H A Dvcn_2_0_0_sh_mask.h2679 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK … macro
H A Dvcn_2_6_0_sh_mask.h36 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK … macro
H A Dvcn_3_0_0_sh_mask.h3741 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK … macro
H A Dvcn_4_0_0_sh_mask.h3987 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK … macro
H A Dvcn_4_0_3_sh_mask.h4022 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK … macro