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Searched refs:cdclk (Results 1 – 18 of 18) sorted by relevance

/openbsd/sys/dev/pci/drm/i915/display/
H A Dintel_cdclk.c585 int cdclk = cdclk_config->cdclk; in vlv_set_cdclk() local
674 int cdclk = cdclk_config->cdclk; in chv_set_cdclk() local
793 int cdclk = cdclk_config->cdclk; in bdw_set_cdclk() local
1075 int cdclk = cdclk_config->cdclk; in skl_set_cdclk() local
1410 table[i].cdclk == cdclk) in bxt_calc_cdclk_pll_vco()
1726 table[i].cdclk == cdclk) in cdclk_squash_waveform()
1852 int cdclk = cdclk_config->cdclk; in _bxt_set_cdclk() local
2008 if (cdclk != dev_priv->display.cdclk.hw.cdclk) in bxt_sanitize_cdclk()
2175 return a->cdclk != b->cdclk && in intel_cdclk_can_squash()
2194 return a->cdclk != b->cdclk || in intel_cdclk_needs_modeset()
[all …]
H A Dintel_cdclk.h19 unsigned int cdclk, vco, ref, bypass; member
83 …k_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))
85 …k_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))
H A Dintel_audio.c427 unsigned int fec_coeff, cdclk, vdsc_bpp; in calc_hblank_early_prog() local
435 cdclk = i915->display.cdclk.hw.cdclk; in calc_hblank_early_prog()
443 h_active, link_clk, lanes, vdsc_bpp, cdclk); in calc_hblank_early_prog()
445 if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bpp || !cdclk)) in calc_hblank_early_prog()
454 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk), in calc_hblank_early_prog()
455 mul_u32_u32(link_clk, cdclk)); in calc_hblank_early_prog()
887 static void get_aud_ts_cdclk_m_n(int refclk, int cdclk, struct aud_ts_cdclk_m_n *aud_ts) in get_aud_ts_cdclk_m_n() argument
890 aud_ts->n = cdclk * aud_ts->m / 24000; in get_aud_ts_cdclk_m_n()
898 get_aud_ts_cdclk_m_n(i915->display.cdclk.hw.ref, i915->display.cdclk.hw.cdclk, &aud_ts); in intel_audio_cdclk_change_post()
1044 return i915->display.cdclk.hw.cdclk; in i915_audio_component_get_cdclk_freq()
H A Dintel_display_driver.c88 cdclk_state = to_intel_cdclk_state(i915->display.cdclk.obj.state); in intel_display_driver_init_hw()
91 intel_cdclk_dump_config(i915, &i915->display.cdclk.hw, "Current CDCLK"); in intel_display_driver_init_hw()
92 cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw; in intel_display_driver_init_hw()
315 if (i915->display.cdclk.max_cdclk_freq == 0) in intel_display_driver_probe_nogem()
H A Dintel_display_core.h278 const struct intel_cdclk_funcs *cdclk; member
336 } cdclk; member
H A Dhsw_ips.c209 crtc_state->pixel_rate > i915->display.cdclk.max_cdclk_freq * 95 / 100) in hsw_crtc_state_ips_capable()
248 if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100) in hsw_ips_compute_config()
H A Dintel_pmdemand.c292 (new_cdclk_state->actual.cdclk != in intel_pmdemand_needs_update()
293 old_cdclk_state->actual.cdclk || in intel_pmdemand_needs_update()
348 DIV_ROUND_UP(new_cdclk_state->actual.cdclk, 1000); in intel_pmdemand_atomic_check()
H A Dintel_dp_aux.c89 freq = dev_priv->display.cdclk.hw.cdclk; in ilk_get_aux_clock_divider()
H A Dintel_modeset_setup.c159 to_intel_cdclk_state(i915->display.cdclk.obj.state); in intel_crtc_disable_noatomic_complete()
679 to_intel_cdclk_state(i915->display.cdclk.obj.state); in intel_modeset_readout_hw_state()
H A Dintel_backlight.c1110 clock = KHz(i915->display.cdclk.hw.cdclk); in i9xx_hz_to_pwm()
1128 clock = KHz(i915->display.cdclk.hw.cdclk); in i965_hz_to_pwm()
H A Dintel_fbc.c1167 if (crtc_state->pixel_rate >= cdclk_state->logical.cdclk * 95 / 100) { in intel_fbc_check_plane()
H A Dintel_display_power_well.c982 intel_cdclk_needs_modeset(&dev_priv->display.cdclk.hw, in gen9_disable_dc_states()
H A Dintel_dpll_mgr.c1873 i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; in skl_update_dpll_ref_clks()
3945 i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; in icl_update_dpll_ref_clks()
H A Dintel_display_power.c1369 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); in hsw_restore_lcpll()
H A Dintel_dp.c796 i915->display.cdclk.max_cdclk_freq * 48 / in intel_dp_dsc_get_output_bpp()
830 if (mode_clock >= ((i915->display.cdclk.max_cdclk_freq * 85) / 100)) in intel_dp_dsc_get_slice_count()
H A Dintel_display.c2305 clock_limit = i915->display.cdclk.max_cdclk_freq * 9 / 10; in intel_crtc_compute_pipe_mode()
4207 cdclk_state->logical.cdclk); in hsw_ips_linetime_wm()
/openbsd/sys/dev/pci/drm/i915/gt/
H A Dintel_gt_pm_debugfs.c398 drm_printf(p, "Current CD clock frequency: %d kHz\n", i915->display.cdclk.hw.cdclk); in intel_gt_pm_frequency_dump()
399 drm_printf(p, "Max CD clock frequency: %d kHz\n", i915->display.cdclk.max_cdclk_freq); in intel_gt_pm_frequency_dump()
/openbsd/sys/dev/pci/drm/i915/
H A Di915_reg.h5399 #define DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes, voltage_level) \ argument
5400 ((DISPLAY_TO_PCODE_CDCLK(cdclk)) | \