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Searched refs:cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL (Results 1 – 3 of 3) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/nbio/
H A Dnbio_6_1_offset.h789 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL … macro
H A Dnbio_7_4_offset.h1048 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL … macro
H A Dnbio_2_3_offset.h2161 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL … macro