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Searched refs:cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL (Results 1 – 3 of 3) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/nbio/
H A Dnbio_6_1_offset.h750 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL … macro
H A Dnbio_7_4_offset.h1009 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL … macro
H A Dnbio_2_3_offset.h2122 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL … macro