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Searched refs:clocks (Results 1 – 25 of 79) sorted by relevance

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/openbsd/sys/dev/ofw/
H A Dofw_clock.c143 uint32_t *clocks; in clock_get_frequency_idx() local
155 clock = clocks; in clock_get_frequency_idx()
165 free(clocks, M_TEMP, len); in clock_get_frequency_idx()
184 uint32_t *clocks; in clock_set_frequency_idx() local
196 clock = clocks; in clock_set_frequency_idx()
206 free(clocks, M_TEMP, len); in clock_set_frequency_idx()
225 uint32_t *clocks; in clock_do_enable_idx() local
236 clock = clocks; in clock_do_enable_idx()
246 free(clocks, M_TEMP, len); in clock_do_enable_idx()
288 uint32_t *clocks, *parents, *rates; in clock_set_assigned() local
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/openbsd/sys/dev/pci/drm/amd/pm/powerplay/
H A Damd_powerplay.c1057 struct amd_pp_clock_info *clocks) in pp_get_current_clocks() argument
1093 clocks->max_clocks_state = PP_DAL_POWERLEVEL_7; in pp_get_current_clocks()
1111 if (clocks == NULL) in pp_get_clock_by_type()
1119 struct pp_clock_levels_with_latency *clocks) in pp_get_clock_by_type_with_latency() argument
1123 if (!hwmgr || !hwmgr->pm_en || !clocks) in pp_get_clock_by_type_with_latency()
1131 struct pp_clock_levels_with_voltage *clocks) in pp_get_clock_by_type_with_voltage() argument
1135 if (!hwmgr || !hwmgr->pm_en || !clocks) in pp_get_clock_by_type_with_voltage()
1165 struct amd_pp_simple_clock_info *clocks) in pp_get_display_mode_validation_clocks() argument
1170 if (!hwmgr || !hwmgr->pm_en || !clocks) in pp_get_display_mode_validation_clocks()
1173 clocks->level = PP_DAL_POWERLEVEL_7; in pp_get_display_mode_validation_clocks()
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/openbsd/usr.bin/telnet/
H A Ddefines.h42 extern Clocks clocks;
44 #define settimer(x) clocks.x = clocks.system++
H A Dterminal.c144 if (dontlecho && (clocks.echotoggle > clocks.modenegotiated)) { in getconnmode()
/openbsd/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/
H A Dhardwaremanager.c429 …et_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks) in phm_get_clock_by_type() argument
436 return hwmgr->hwmgr_func->get_clock_by_type(hwmgr, type, clocks); in phm_get_clock_by_type()
442 struct pp_clock_levels_with_latency *clocks) in phm_get_clock_by_type_with_latency() argument
449 return hwmgr->hwmgr_func->get_clock_by_type_with_latency(hwmgr, type, clocks); in phm_get_clock_by_type_with_latency()
455 struct pp_clock_levels_with_voltage *clocks) in phm_get_clock_by_type_with_voltage() argument
462 return hwmgr->hwmgr_func->get_clock_by_type_with_voltage(hwmgr, type, clocks); in phm_get_clock_by_type_with_voltage()
489 int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks) in phm_get_max_high_clocks() argument
496 return hwmgr->hwmgr_func->get_max_high_clocks(hwmgr, clocks); in phm_get_max_high_clocks()
H A Dvega12_hwmgr.c1861 clocks->data[i].clocks_in_khz = in vega12_get_sclks()
1864 clocks->data[i].latency_in_us = 0; in vega12_get_sclks()
1867 clocks->num_levels = ucount; in vega12_get_sclks()
1895 clocks->data[i].latency_in_us = in vega12_get_memclocks()
1922 clocks->data[i].clocks_in_khz = in vega12_get_dcefclocks()
1925 clocks->data[i].latency_in_us = 0; in vega12_get_dcefclocks()
1928 clocks->num_levels = ucount; in vega12_get_dcefclocks()
1950 clocks->data[i].clocks_in_khz = in vega12_get_socclocks()
1953 clocks->data[i].latency_in_us = 0; in vega12_get_socclocks()
1956 clocks->num_levels = ucount; in vega12_get_socclocks()
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H A Dsmu10_hwmgr.c191 struct PP_Clocks clocks = {0}; in smu10_set_clock_limit() local
1164 struct pp_clock_levels_with_latency *clocks) in smu10_get_clock_by_type_with_latency() argument
1203 clocks->num_levels = 0; in smu10_get_clock_by_type_with_latency()
1206 clocks->data[clocks->num_levels].clocks_in_khz = in smu10_get_clock_by_type_with_latency()
1208 clocks->data[clocks->num_levels].latency_in_us = latency_required ? in smu10_get_clock_by_type_with_latency()
1212 clocks->num_levels++; in smu10_get_clock_by_type_with_latency()
1221 struct pp_clock_levels_with_voltage *clocks) in smu10_get_clock_by_type_with_voltage() argument
1257 clocks->num_levels = 0; in smu10_get_clock_by_type_with_voltage()
1260 clocks->data[clocks->num_levels].clocks_in_khz = pclk_vol_table->entries[i].clk * 10; in smu10_get_clock_by_type_with_voltage()
1261 clocks->data[clocks->num_levels].voltage_in_mv = pclk_vol_table->entries[i].vol; in smu10_get_clock_by_type_with_voltage()
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H A Dsmu8_hwmgr.c1075 struct PP_Clocks clocks = {0, 0, 0, 0}; in smu8_apply_state_adjust_rules() local
1647 struct amd_pp_clocks *clocks) in smu8_get_clock_by_type() argument
1653 clocks->count = smu8_get_max_sclk_level(hwmgr); in smu8_get_clock_by_type()
1656 for (i = 0; i < clocks->count; i++) in smu8_get_clock_by_type()
1661 for (i = 0; i < clocks->count; i++) in smu8_get_clock_by_type()
1662 clocks->clock[i] = table->entries[i].clk * 10; in smu8_get_clock_by_type()
1665 clocks->count = SMU8_NUM_NBPMEMORYCLOCK; in smu8_get_clock_by_type()
1666 for (i = 0; i < clocks->count; i++) in smu8_get_clock_by_type()
1667 clocks->clock[i] = data->sys_info.nbp_memory_clock[clocks->count - 1 - i] * 10; in smu8_get_clock_by_type()
1690 clocks->engine_max_clock = table->entries[level].clk; in smu8_get_max_high_clocks()
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H A Dvega20_hwmgr.c2815 clocks->num_levels = count; in vega20_get_sclks()
2818 clocks->data[i].clocks_in_khz = in vega20_get_sclks()
2820 clocks->data[i].latency_in_us = 0; in vega20_get_sclks()
2846 clocks->data[i].clocks_in_khz = in vega20_get_memclocks()
2849 clocks->data[i].latency_in_us = in vega20_get_memclocks()
2868 clocks->num_levels = count; in vega20_get_dcefclocks()
2871 clocks->data[i].clocks_in_khz = in vega20_get_dcefclocks()
2873 clocks->data[i].latency_in_us = 0; in vega20_get_dcefclocks()
2890 clocks->num_levels = count; in vega20_get_socclocks()
2893 clocks->data[i].clocks_in_khz = in vega20_get_socclocks()
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/openbsd/sys/dev/pci/drm/amd/pm/swsmu/smu13/
H A Daldebaran_ppt.c562 clocks->num_levels = min_t(uint32_t, in aldebaran_get_clk_table()
566 for (i = 0; i < clocks->num_levels; i++) { in aldebaran_get_clk_table()
567 clocks->data[i].clocks_in_khz = in aldebaran_get_clk_table()
569 clocks->data[i].latency_in_us = 0; in aldebaran_get_clk_table()
828 for (i = 0; i < clocks.num_levels; i++) in aldebaran_print_clk_levels()
831 (clocks.num_levels == 1) ? "*" : in aldebaran_print_clk_levels()
851 for (i = 0; i < clocks.num_levels; i++) in aldebaran_print_clk_levels()
854 (clocks.num_levels == 1) ? "*" : in aldebaran_print_clk_levels()
877 (clocks.num_levels == 1) ? "*" : in aldebaran_print_clk_levels()
900 (clocks.num_levels == 1) ? "*" : in aldebaran_print_clk_levels()
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H A Dsmu_v13_0_6_ppt.c645 clocks->num_levels = count; in smu_v13_0_6_get_clk_table()
648 clocks->data[i].clocks_in_khz = in smu_v13_0_6_get_clk_table()
650 clocks->data[i].latency_in_us = 0; in smu_v13_0_6_get_clk_table()
865 (clocks.num_levels == 1) ? in smu_v13_0_6_print_clk_levels()
868 clocks.data[i].clocks_in_khz / in smu_v13_0_6_print_clk_levels()
896 (clocks.num_levels == 1) ? in smu_v13_0_6_print_clk_levels()
899 clocks.data[i].clocks_in_khz / in smu_v13_0_6_print_clk_levels()
927 (clocks.num_levels == 1) ? in smu_v13_0_6_print_clk_levels()
930 clocks.data[i].clocks_in_khz / in smu_v13_0_6_print_clk_levels()
958 (clocks.num_levels == 1) ? in smu_v13_0_6_print_clk_levels()
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/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_clk_mgr.c241 cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz; in dcn316_update_clocks()
242 cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz = in dcn316_update_clocks()
244 cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz; in dcn316_update_clocks()
245 cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz; in dcn316_update_clocks()
441 static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks) in find_max_clk_value() argument
447 if (clocks[i] > max) in find_max_clk_value()
448 max = clocks[i]; in find_max_clk_value()
456 const uint32_t clocks[], in find_clk_for_voltage() argument
465 return clocks[i]; in find_clk_for_voltage()
469 clock = clocks[i]; in find_clk_for_voltage()
/openbsd/sys/dev/pci/drm/amd/pm/swsmu/smu11/
H A Darcturus_ppt.c578 clocks->num_levels = min_t(uint32_t, in arcturus_get_clk_table()
583 clocks->data[i].clocks_in_khz = in arcturus_get_clk_table()
585 clocks->data[i].latency_in_us = 0; in arcturus_get_clk_table()
802 (clocks.num_levels == 1) ? "*" : in arcturus_print_clk_levels()
825 (clocks.num_levels == 1) ? "*" : in arcturus_print_clk_levels()
827 clocks.data[i].clocks_in_khz / 1000, in arcturus_print_clk_levels()
848 (clocks.num_levels == 1) ? "*" : in arcturus_print_clk_levels()
850 clocks.data[i].clocks_in_khz / 1000, in arcturus_print_clk_levels()
871 (clocks.num_levels == 1) ? "*" : in arcturus_print_clk_levels()
894 (clocks.num_levels == 1) ? "*" : in arcturus_print_clk_levels()
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/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.c250 cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz; in dcn31_update_clocks()
251 cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz = in dcn31_update_clocks()
253 cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz; in dcn31_update_clocks()
254 cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz; in dcn31_update_clocks()
519 static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks) in find_max_clk_value() argument
525 if (clocks[i] > max) in find_max_clk_value()
526 max = clocks[i]; in find_max_clk_value()
534 const uint32_t clocks[], in find_clk_for_voltage() argument
543 return clocks[i]; in find_clk_for_voltage()
547 clock = clocks[i]; in find_clk_for_voltage()
/openbsd/sys/arch/armv7/exynos/
H A Dexclock.c73 enum clocks { enum
92 uint32_t exclock_decode_pll_clk(enum clocks, unsigned int, unsigned int);
93 uint32_t exclock_get_pll_clk(struct exclock_softc *, enum clocks);
335 exclock_decode_pll_clk(enum clocks pll, unsigned int r, unsigned int k) in exclock_decode_pll_clk()
385 exclock_get_pll_clk(struct exclock_softc *sc, enum clocks pll) in exclock_get_pll_clk()
/openbsd/usr.bin/calendar/calendars/
H A Dcalendar.canada16 03/SunSecond Daylight Saving Time begins; clocks move forward (2nd Sunday of March)
32 11/SunFirst Daylight Saving Time ends; clocks move back (1st Sunday in November)
H A Dcalendar.nz15 04/SunFirst Daylight Saving Time ends; clocks move back (first Sunday of April)
20 09/SunLast Daylight Saving Time starts; clocks move forward (last Sunday in September)
H A Dcalendar.usholiday16 03/SunSecond Daylight Saving Time begins; clocks move forward (2nd Sunday of March)
34 11/SunFirst Daylight Saving Time ends; clocks move back (1st Sunday in November)
H A Dcalendar.uk17 03/SunLast Daylight Saving Time begins; clocks move forward (last Sunday of March)
32 10/SunLast Daylight Saving Time ends; clocks move back (last Sunday in October)
/openbsd/sys/dev/pci/drm/amd/pm/powerplay/inc/
H A Dhardwaremanager.h447 …t_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
451 struct pp_clock_levels_with_latency *clocks);
454 struct pp_clock_levels_with_voltage *clocks);
460 extern int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
/openbsd/sys/dev/pci/drm/amd/pm/inc/
H A Damdgpu_dpm.h531 struct amd_pp_clocks *clocks);
533 struct amd_pp_simple_clock_info *clocks);
536 struct pp_clock_levels_with_latency *clocks);
539 struct pp_clock_levels_with_voltage *clocks);
545 struct amd_pp_clock_info *clocks);
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c278 cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz; in dcn314_update_clocks()
279 cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz = in dcn314_update_clocks()
281 cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz; in dcn314_update_clocks()
282 cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz; in dcn314_update_clocks()
554 static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks) in find_max_clk_value() argument
560 if (clocks[i] > max) in find_max_clk_value()
561 max = clocks[i]; in find_max_clk_value()
/openbsd/sys/dev/pci/drm/amd/include/
H A Dkgd_pp_interface.h379 struct amd_pp_clock_info *clocks);
382 struct amd_pp_clocks *clocks);
385 struct pp_clock_levels_with_latency *clocks);
388 struct pp_clock_levels_with_voltage *clocks);
394 struct amd_pp_simple_clock_info *clocks);
/openbsd/sys/dev/pci/drm/amd/display/dc/dcn32/
H A Ddcn32_hwseq.c737 struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk; in dcn32_initialize_min_clocks() local
739 clocks->dcfclk_deep_sleep_khz = DCN3_2_DCFCLK_DS_INIT_KHZ; in dcn32_initialize_min_clocks()
740 clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000; in dcn32_initialize_min_clocks()
741 clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000; in dcn32_initialize_min_clocks()
742 clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000; in dcn32_initialize_min_clocks()
743 clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000; in dcn32_initialize_min_clocks()
744 clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000; in dcn32_initialize_min_clocks()
745 clocks->fclk_p_state_change_support = true; in dcn32_initialize_min_clocks()
746 clocks->p_state_change_support = true; in dcn32_initialize_min_clocks()
748 clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000; in dcn32_initialize_min_clocks()
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/openbsd/sys/dev/pci/drm/amd/pm/
H A Damdgpu_dpm.c1541 struct amd_pp_clocks *clocks) in amdgpu_dpm_get_clock_by_type() argument
1552 clocks); in amdgpu_dpm_get_clock_by_type()
1559 struct amd_pp_simple_clock_info *clocks) in amdgpu_dpm_get_display_mode_validation_clks() argument
1569 clocks); in amdgpu_dpm_get_display_mode_validation_clks()
1577 struct pp_clock_levels_with_latency *clocks) in amdgpu_dpm_get_clock_by_type_with_latency() argument
1588 clocks); in amdgpu_dpm_get_clock_by_type_with_latency()
1596 struct pp_clock_levels_with_voltage *clocks) in amdgpu_dpm_get_clock_by_type_with_voltage() argument
1607 clocks); in amdgpu_dpm_get_clock_by_type_with_voltage()
1648 struct amd_pp_clock_info *clocks) in amdgpu_dpm_get_current_clocks() argument
1658 clocks); in amdgpu_dpm_get_current_clocks()

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