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Searched refs:mmRLC_GPU_IOV_SMU_RESPONSE (Results 1 – 6 of 6) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_d.h1545 #define mmRLC_GPU_IOV_SMU_RESPONSE 0xfb4a macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h6837 #define mmRLC_GPU_IOV_SMU_RESPONSE … macro
H A Dgc_9_2_1_offset.h7103 #define mmRLC_GPU_IOV_SMU_RESPONSE … macro
H A Dgc_9_1_offset.h7063 #define mmRLC_GPU_IOV_SMU_RESPONSE … macro
H A Dgc_10_1_0_offset.h10419 #define mmRLC_GPU_IOV_SMU_RESPONSE … macro
H A Dgc_10_3_0_offset.h10155 #define mmRLC_GPU_IOV_SMU_RESPONSE … macro