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Searched refs:mmSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX (Results 1 – 4 of 4) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2710 #define mmSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX … macro
H A Dgc_9_2_1_offset.h2896 #define mmSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX … macro
H A Dgc_9_1_offset.h2954 #define mmSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX … macro
H A Dgc_10_1_0_offset.h5192 #define mmSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX … macro