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Searched refs:pipe_config (Results 1 – 25 of 43) sorted by relevance

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/openbsd/sys/dev/pci/drm/i915/display/
H A Dintel_crtc_state_dump.c229 pipe_config->pipe_bpp, pipe_config->dither); in intel_crtc_state_dump()
271 pipe_config->has_audio, pipe_config->has_infoframe, in intel_crtc_state_dump()
303 pipe_config->vrr.vmin, pipe_config->vrr.vmax, in intel_crtc_state_dump()
304 pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband, in intel_crtc_state_dump()
323 pipe_config->linetime, pipe_config->ips_linetime); in intel_crtc_state_dump()
347 pipe_config->ips_enabled, pipe_config->double_wide, in intel_crtc_state_dump()
355 pipe_config->cgm_mode, pipe_config->gamma_mode, in intel_crtc_state_dump()
356 pipe_config->gamma_enable, pipe_config->csc_enable); in intel_crtc_state_dump()
360 pipe_config->csc_mode, pipe_config->gamma_mode, in intel_crtc_state_dump()
361 pipe_config->gamma_enable, pipe_config->csc_enable); in intel_crtc_state_dump()
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H A Dg4x_hdmi.c174 pipe_config->infoframes.enable |= in intel_hdmi_get_config()
181 pipe_config->has_audio = true; in intel_hdmi_get_config()
194 if (pipe_config->pixel_multiplier) in intel_hdmi_get_config()
199 pipe_config->lane_count = 4; in intel_hdmi_get_config()
227 if (pipe_config->has_audio) in g4x_hdmi_enable_port()
244 !pipe_config->has_hdmi_sink); in g4x_enable_hdmi()
261 if (pipe_config->has_audio) in ibx_enable_hdmi()
280 if (pipe_config->pipe_bpp > 24 && in ibx_enable_hdmi()
316 if (pipe_config->has_audio) in cpt_enable_hdmi()
329 if (pipe_config->pipe_bpp > 24) { in cpt_enable_hdmi()
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H A Dg4x_dp.c80 pipe_config->dpll = divisor[i]; in g4x_dp_set_clock()
81 pipe_config->clock_set = true; in g4x_dp_set_clock()
98 pipe_config->port_clock, in intel_dp_prepare()
99 pipe_config->lane_count); in intel_dp_prepare()
156 if (pipe_config->enhanced_framing) in intel_dp_prepare()
201 pipe_config->port_clock); in ilk_edp_pll_on()
386 pipe_config->lane_count = in intel_dp_get_config()
389 g4x_dp_get_m_n(pipe_config); in intel_dp_get_config()
393 pipe_config->port_clock = 162000; in intel_dp_get_config()
395 pipe_config->port_clock = 270000; in intel_dp_get_config()
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H A Dintel_modeset_verify.c90 const struct intel_crtc_state *pipe_config) in intel_pipe_config_sanity_check() argument
92 if (pipe_config->has_pch_encoder) { in intel_pipe_config_sanity_check()
94 &pipe_config->fdi_m_n); in intel_pipe_config_sanity_check()
166 struct intel_crtc_state *pipe_config = old_crtc_state; in verify_crtc_state() local
178 pipe_config->hw.enable = new_crtc_state->hw.enable; in verify_crtc_state()
180 intel_crtc_get_pipe_config(pipe_config); in verify_crtc_state()
183 if (IS_I830(dev_priv) && pipe_config->hw.active) in verify_crtc_state()
184 pipe_config->hw.active = new_crtc_state->hw.active; in verify_crtc_state()
189 new_crtc_state->hw.active, pipe_config->hw.active); in verify_crtc_state()
212 intel_encoder_get_config(encoder, pipe_config); in verify_crtc_state()
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H A Dintel_dp_mst.c313 &pipe_config->hw.adjusted_mode; in intel_dp_mst_compute_config()
322 pipe_config->has_pch_encoder = false; in intel_dp_mst_compute_config()
324 pipe_config->has_audio = in intel_dp_mst_compute_config()
373 pipe_config->dp_m_n.tu, false); in intel_dp_mst_compute_config()
383 pipe_config->limited_color_range = in intel_dp_mst_compute_config()
387 pipe_config->lane_lat_optim_mask = in intel_dp_mst_compute_config()
676 pipe_config, NULL); in intel_mst_pre_pll_enable_dp()
722 pipe_config, NULL); in intel_mst_pre_enable_dp()
763 if (intel_dp_is_uhbr(pipe_config)) { in intel_mst_enable_dp()
765 &pipe_config->hw.adjusted_mode; in intel_mst_enable_dp()
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H A Dintel_dp.c1785 if (pipe_config->bigjoiner_pipes || pipe_config->dsc.slice_count > 1) in intel_dp_dsc_compute_config()
1793 pipe_config->pipe_bpp, in intel_dp_dsc_compute_config()
1801 pipe_config->pipe_bpp, in intel_dp_dsc_compute_config()
1882 pipe_config->lane_count, pipe_config->port_clock, in intel_dp_compute_link_config()
1883 pipe_config->pipe_bpp, in intel_dp_compute_link_config()
1894 pipe_config->lane_count, pipe_config->port_clock, in intel_dp_compute_link_config()
2131 if (pipe_config->has_psr) in can_enable_drrs()
2178 pipe_config->port_clock, &pipe_config->dp_m2_n2, in intel_dp_drrs_compute_config()
2183 pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count; in intel_dp_drrs_compute_config()
2280 pipe_config->has_audio = in intel_dp_compute_config()
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H A Dintel_crt.c147 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_crt_get_config()
153 lpt_pch_get_config(pipe_config); in hsw_crt_get_config()
399 &pipe_config->hw.adjusted_mode; in intel_crt_compute_config()
415 &pipe_config->hw.adjusted_mode; in pch_crt_compute_config()
420 pipe_config->has_pch_encoder = true; in pch_crt_compute_config()
432 &pipe_config->hw.adjusted_mode; in hsw_crt_compute_config()
442 pipe_config->has_pch_encoder = true; in hsw_crt_compute_config()
447 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { in hsw_crt_compute_config()
453 pipe_config->pipe_bpp = 24; in hsw_crt_compute_config()
457 pipe_config->port_clock = 135000 * 2; in hsw_crt_compute_config()
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H A Dintel_display.c2905 pipe_config->sink_format = pipe_config->output_format; in i9xx_get_pipe_config()
3009 pipe_config->port_clock / pipe_config->pixel_multiplier; in i9xx_get_pipe_config()
3311 pipe_config->pipe_bpp = 18; in ilk_get_pipe_config()
3314 pipe_config->pipe_bpp = 24; in ilk_get_pipe_config()
3317 pipe_config->pipe_bpp = 30; in ilk_get_pipe_config()
3320 pipe_config->pipe_bpp = 36; in ilk_get_pipe_config()
3339 pipe_config->sink_format = pipe_config->output_format; in ilk_get_pipe_config()
3739 pipe_config->sink_format = pipe_config->output_format; in hsw_get_pipe_config()
3764 pipe_config->ips_linetime = in hsw_get_pipe_config()
3954 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) in intel_crtc_dotclock()
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H A Dintel_dvo.c158 struct intel_crtc_state *pipe_config) in intel_dvo_get_config() argument
164 pipe_config->output_types |= BIT(INTEL_OUTPUT_DVO); in intel_dvo_get_config()
176 pipe_config->hw.adjusted_mode.flags |= flags; in intel_dvo_get_config()
178 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_dvo_get_config()
198 const struct intel_crtc_state *pipe_config, in intel_enable_dvo() argument
206 &pipe_config->hw.mode, in intel_enable_dvo()
207 &pipe_config->hw.adjusted_mode); in intel_enable_dvo()
254 struct intel_crtc_state *pipe_config, in intel_dvo_compute_config() argument
280 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; in intel_dvo_compute_config()
281 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in intel_dvo_compute_config()
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H A Dintel_fdi.c142 if (pipe_config->fdi_lanes > 4) { in ilk_check_fdi_lanes()
150 if (pipe_config->fdi_lanes > 2) { in ilk_check_fdi_lanes()
153 pipe_config->fdi_lanes); in ilk_check_fdi_lanes()
168 if (pipe_config->fdi_lanes <= 2) in ilk_check_fdi_lanes()
185 if (pipe_config->fdi_lanes > 2) { in ilk_check_fdi_lanes()
236 struct intel_crtc_state *pipe_config) in ilk_fdi_compute_config() argument
257 pipe_config->pipe_bpp); in ilk_fdi_compute_config()
259 pipe_config->fdi_lanes = lane; in ilk_fdi_compute_config()
269 pipe_config->pipe_bpp -= 2*3; in ilk_fdi_compute_config()
272 pipe_config->pipe_bpp); in ilk_fdi_compute_config()
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H A Dvlv_dsi.c300 pipe_config->pipe_bpp = 24; in intel_dsi_compute_config()
302 pipe_config->pipe_bpp = 18; in intel_dsi_compute_config()
306 pipe_config->mode_flags |= in intel_dsi_compute_config()
324 pipe_config->clock_set = true; in intel_dsi_compute_config()
743 bxt_dsi_pll_enable(encoder, pipe_config); in intel_dsi_pre_enable()
765 intel_dsi_prepare(encoder, pipe_config); in intel_dsi_pre_enable()
785 intel_dsi_prepare(encoder, pipe_config); in intel_dsi_pre_enable()
1012 &pipe_config->hw.adjusted_mode; in bxt_dsi_get_pipe_config()
1043 pipe_config->mode_flags |= in bxt_dsi_get_pipe_config()
1170 struct intel_crtc_state *pipe_config) in intel_dsi_get_config() argument
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H A Dicl_dsi.c302 &pipe_config->hw.adjusted_mode; in configure_dual_link_mode()
1189 gen11_dsi_map_pll(encoder, pipe_config); in gen11_dsi_pre_enable()
1455 struct intel_crtc_state *pipe_config) in gen11_dsi_get_timings() argument
1459 &pipe_config->hw.adjusted_mode; in gen11_dsi_get_timings()
1461 if (pipe_config->dsc.compressed_bpp) { in gen11_dsi_get_timings()
1522 struct intel_crtc_state *pipe_config) in gen11_dsi_get_config() argument
1623 &pipe_config->hw.adjusted_mode; in gen11_dsi_compute_config()
1646 pipe_config->pipe_bpp = 24; in gen11_dsi_compute_config()
1648 pipe_config->pipe_bpp = 18; in gen11_dsi_compute_config()
1650 pipe_config->clock_set = true; in gen11_dsi_compute_config()
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H A Dintel_ddi.c3676 pipe_config->pipe_bpp = 18; in intel_ddi_read_func_ctl()
3679 pipe_config->pipe_bpp = 24; in intel_ddi_read_func_ctl()
3682 pipe_config->pipe_bpp = 30; in intel_ddi_read_func_ctl()
3685 pipe_config->pipe_bpp = 36; in intel_ddi_read_func_ctl()
3709 pipe_config->lane_count = in intel_ddi_read_func_ctl()
3719 pipe_config->lane_count = in intel_ddi_read_func_ctl()
3732 pipe_config->fec_enable = in intel_ddi_read_func_ctl()
3755 pipe_config->lane_count = in intel_ddi_read_func_ctl()
3787 pipe_config->has_audio = in intel_ddi_get_config()
4065 pipe_config->has_hdmi_sink = in intel_ddi_compute_config()
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H A Dintel_pipe_crc.c282 struct intel_crtc_state *pipe_config; in intel_crtc_crc_setup_workarounds() local
299 pipe_config = intel_atomic_get_crtc_state(state, crtc); in intel_crtc_crc_setup_workarounds()
300 if (IS_ERR(pipe_config)) { in intel_crtc_crc_setup_workarounds()
301 ret = PTR_ERR(pipe_config); in intel_crtc_crc_setup_workarounds()
305 pipe_config->uapi.mode_changed = pipe_config->has_psr; in intel_crtc_crc_setup_workarounds()
306 pipe_config->crc_enabled = enable; in intel_crtc_crc_setup_workarounds()
309 pipe_config->hw.active && crtc->pipe == PIPE_A && in intel_crtc_crc_setup_workarounds()
310 pipe_config->cpu_transcoder == TRANSCODER_EDP) in intel_crtc_crc_setup_workarounds()
311 pipe_config->uapi.mode_changed = true; in intel_crtc_crc_setup_workarounds()
H A Dintel_sdvo.c1300 pipe_config->clock_set = true; in i9xx_adjust_sdvo_tv_clock()
1356 pipe_config->pipe_bpp = 8*3; in intel_sdvo_compute_config()
1377 pipe_config->sdvo_tv_clock = true; in intel_sdvo_compute_config()
1404 pipe_config->pixel_multiplier = in intel_sdvo_compute_config()
1409 pipe_config->has_audio = in intel_sdvo_compute_config()
1413 pipe_config->limited_color_range = in intel_sdvo_compute_config()
1721 pipe_config->pixel_multiplier = in intel_sdvo_get_config()
1726 dotclock = pipe_config->port_clock; in intel_sdvo_get_config()
1728 if (pipe_config->pixel_multiplier) in intel_sdvo_get_config()
1763 pipe_config->has_audio = true; in intel_sdvo_get_config()
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H A Dintel_tv.c926 const struct intel_crtc_state *pipe_config, in intel_enable_tv() argument
1094 struct intel_crtc_state *pipe_config) in intel_tv_get_config() argument
1098 &pipe_config->hw.adjusted_mode; in intel_tv_get_config()
1128 tv_mode.clock = pipe_config->port_clock; in intel_tv_get_config()
1171 pipe_config->mode_flags |= in intel_tv_get_config()
1193 struct intel_crtc_state *pipe_config, in intel_tv_compute_config() argument
1204 &pipe_config->hw.adjusted_mode; in intel_tv_compute_config()
1219 pipe_config->pipe_bpp = 8*3; in intel_tv_compute_config()
1221 pipe_config->port_clock = tv_mode->clock; in intel_tv_compute_config()
1227 pipe_config->clock_set = true; in intel_tv_compute_config()
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H A Dintel_vdsc.c220 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_RGB || in intel_dsc_slice_dimensions_valid()
221 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) { in intel_dsc_slice_dimensions_valid()
240 int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) in intel_dsc_compute_params() argument
242 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_dsc_compute_params()
244 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; in intel_dsc_compute_params()
245 u16 compressed_bpp = pipe_config->dsc.compressed_bpp; in intel_dsc_compute_params()
251 pipe_config->dsc.slice_count); in intel_dsc_compute_params()
253 err = intel_dsc_slice_dimensions_valid(pipe_config, vdsc_cfg); in intel_dsc_compute_params()
265 pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR444; in intel_dsc_compute_params()
268 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) in intel_dsc_compute_params()
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H A Dintel_hdmi.c253 const struct intel_crtc_state *pipe_config) in g4x_infoframes_enabled() argument
2303 if (pipe_config->has_hdmi_sink) in intel_hdmi_compute_config()
2304 pipe_config->has_infoframe = true; in intel_hdmi_compute_config()
2307 pipe_config->pixel_multiplier = 2; in intel_hdmi_compute_config()
2309 pipe_config->has_audio = in intel_hdmi_compute_config()
2327 if (intel_hdmi_is_ycbcr420(pipe_config)) { in intel_hdmi_compute_config()
2333 pipe_config->limited_color_range = in intel_hdmi_compute_config()
2340 pipe_config->lane_count = 4; in intel_hdmi_compute_config()
2344 pipe_config->hdmi_scrambling = true; in intel_hdmi_compute_config()
2346 if (pipe_config->port_clock > 340000) { in intel_hdmi_compute_config()
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H A Dintel_lspcon.h35 const struct intel_crtc_state *pipe_config);
37 const struct intel_crtc_state *pipe_config);
H A Dintel_fdi.h16 const struct intel_crtc_state *pipe_config);
18 struct intel_crtc_state *pipe_config);
H A Dintel_dp.h36 struct intel_crtc_state *pipe_config,
62 struct intel_crtc_state *pipe_config,
65 struct intel_crtc_state *pipe_config,
H A Dg4x_dp.h24 struct intel_crtc_state *pipe_config);
H A Dintel_vdsc.h20 int intel_dsc_compute_params(struct intel_crtc_state *pipe_config);
H A Dintel_lspcon.c612 const struct intel_crtc_state *pipe_config) in lspcon_infoframes_enabled() argument
631 HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); in lspcon_infoframes_enabled()
678 const struct intel_crtc_state *pipe_config) in intel_lspcon_infoframes_enabled() argument
682 return dig_port->infoframes_enabled(encoder, pipe_config); in intel_lspcon_infoframes_enabled()
/openbsd/sys/dev/pci/drm/amd/display/dc/
H A Ddc_dmub_srv.c466 pipe_data->pipe_config.vblank_data.drr_info.drr_in_use = true; in populate_subvp_cmd_drr_info()
552 pipe_data->pipe_config.vblank_data.vblank_end = in populate_subvp_cmd_vblank_pipe_info()
597 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = in update_subvp_prefetch_end_to_mall_start()
605 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = in update_subvp_prefetch_end_to_mall_start()
642 pipe_data->pipe_config.subvp_data.main_vblank_start = in populate_subvp_cmd_pipe_info()
644 pipe_data->pipe_config.subvp_data.main_vblank_end = in populate_subvp_cmd_pipe_info()
665 pipe_data->pipe_config.subvp_data.prefetch_lines = in populate_subvp_cmd_pipe_info()
669 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = in populate_subvp_cmd_pipe_info()
672 pipe_data->pipe_config.subvp_data.processing_delay_lines = in populate_subvp_cmd_pipe_info()
681 pipe_data->pipe_config.subvp_data.main_split_pipe_index = 0; in populate_subvp_cmd_pipe_info()
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