Searched refs:post_divider (Results 1 – 14 of 14) sorted by relevance
50 u32 reference_divider, post_divider; in rv730_populate_sclk_value() local62 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_sclk_value()65 post_divider = 1; in rv730_populate_sclk_value()67 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv730_populate_sclk_value()90 u32 vco_freq = engine_clock * post_divider; in rv730_populate_sclk_value()129 u32 post_divider, reference_divider; in rv730_populate_mclk_value() local140 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_mclk_value()143 post_divider = 1; in rv730_populate_mclk_value()165 u32 vco_freq = memory_clock * post_divider; in rv730_populate_mclk_value()
152 step->post_divider = 1; in rv6xx_convert_clock_to_stepping()173 if (step->post_divider == 1) in rv6xx_output_stepping()176 u32 lo_len = (step->post_divider - 2) / 2; in rv6xx_output_stepping()199 next.post_divider = cur->post_divider; in rv6xx_next_vco_step()213 return (cur->post_divider > target->post_divider) && in rv6xx_can_step_post_div()225 next.post_divider--; in rv6xx_next_post_div_step()255 if (target.post_divider > cur.post_divider) in rv6xx_generate_steps()256 cur.post_divider = target.post_divider; in rv6xx_generate_steps()269 tiny.post_divider = next.post_divider; in rv6xx_generate_steps()274 if ((next.post_divider != target.post_divider) && in rv6xx_generate_steps()[all …]
34 u32 post_divider; member
742 uint32_t post_divider = 0; in radeon_set_pll() local820 &reference_div, &post_divider); in radeon_set_pll()823 if (post_div->divider == post_divider) in radeon_set_pll()834 post_divider); in radeon_set_pll()
326 u32 post_divider, reference_divider, feedback_divider8; in rv770_calculate_fractional_mpll_feedback_divider() local334 post_divider = dividers->post_div; in rv770_calculate_fractional_mpll_feedback_divider()338 (8 * fyclk * reference_divider * post_divider) / reference_clock; in rv770_calculate_fractional_mpll_feedback_divider()503 u32 reference_divider, post_divider; in rv770_populate_sclk_value() local515 post_divider = (0x0f & (dividers.post_div >> 4)) + (0x0f & dividers.post_div) + 2; in rv770_populate_sclk_value()517 post_divider = 1; in rv770_populate_sclk_value()519 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv770_populate_sclk_value()541 u32 vco_freq = engine_clock * post_divider; in rv770_populate_sclk_value()
563 u32 post_divider; member
2634 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider; in ci_populate_smc_uvd_level()2642 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider; in ci_populate_smc_uvd_level()2675 table->VceLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_vce_level()2708 table->AcpLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_acp_level()2740 table->SamuLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_samu_level()2979 table->ACPILevel.SclkDid = (u8)dividers.post_divider; in ci_populate_smc_acpi_level()3171 sclk->SclkDid = (u8)dividers.post_divider; in ci_calculate_sclk_params()
2939 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; in radeon_atom_get_clock_dividers()2956 dividers->post_divider = args.v6_out.ulClock.ucPostDiv; in radeon_atom_get_clock_dividers()
9423 tmp |= dividers.post_divider; in cik_set_uvd_clock()9470 tmp |= dividers.post_divider; in cik_set_vce_clocks()
136 uint32_t post_divider, in calculate_fb_and_fractional_fb_divider() argument143 (uint64_t)target_pix_clk_100hz * ref_divider * post_divider; in calculate_fb_and_fractional_fb_divider()195 uint32_t post_divider, in calc_fb_divider_checking_tolerance() argument208 post_divider, in calc_fb_divider_checking_tolerance()219 ref_divider * post_divider * in calc_fb_divider_checking_tolerance()237 pll_settings->pix_clk_post_divider = post_divider; in calc_fb_divider_checking_tolerance()257 uint32_t post_divider; in calc_pll_dividers_in_range() local268 post_divider = max_post_divider; in calc_pll_dividers_in_range()269 post_divider >= min_post_divider; in calc_pll_dividers_in_range()270 --post_divider) { in calc_pll_dividers_in_range()[all …]
49 u32 post_divider; member
1467 tmp |= dividers.post_divider; in cik_set_uvd_clock()1516 tmp |= dividers.post_divider; in cik_set_vce_clocks()
1001 tmp |= dividers.post_divider; in vi_set_uvd_clock()1091 tmp |= dividers.post_divider; in vi_set_vce_clocks()
1061 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; in amdgpu_atombios_get_clock_dividers()1078 dividers->post_divider = args.v6_out.ulClock.ucPostDiv; in amdgpu_atombios_get_clock_dividers()