Home
last modified time | relevance | path

Searched refs:ref_and_mask (Results 1 – 16 of 16) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Dsdma_v2_4.c276 u32 ref_and_mask = 0; in sdma_v2_4_ring_emit_hdp_flush() local
279 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); in sdma_v2_4_ring_emit_hdp_flush()
281 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); in sdma_v2_4_ring_emit_hdp_flush()
288 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v2_4_ring_emit_hdp_flush()
289 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v2_4_ring_emit_hdp_flush()
H A Dsdma_v3_0.c450 u32 ref_and_mask = 0; in sdma_v3_0_ring_emit_hdp_flush() local
453 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); in sdma_v3_0_ring_emit_hdp_flush()
455 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); in sdma_v3_0_ring_emit_hdp_flush()
462 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v3_0_ring_emit_hdp_flush()
463 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v3_0_ring_emit_hdp_flush()
H A Damdgpu_cik_sdma.c249 u32 ref_and_mask; in cik_sdma_ring_emit_hdp_flush() local
252 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK; in cik_sdma_ring_emit_hdp_flush()
254 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK; in cik_sdma_ring_emit_hdp_flush()
259 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in cik_sdma_ring_emit_hdp_flush()
260 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in cik_sdma_ring_emit_hdp_flush()
H A Dsdma_v5_0.c484 u32 ref_and_mask = 0; in sdma_v5_0_ring_emit_hdp_flush() local
488 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0; in sdma_v5_0_ring_emit_hdp_flush()
490 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1; in sdma_v5_0_ring_emit_hdp_flush()
497 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v5_0_ring_emit_hdp_flush()
498 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v5_0_ring_emit_hdp_flush()
H A Dsdma_v6_0.c310 u32 ref_and_mask = 0; in sdma_v6_0_ring_emit_hdp_flush() local
313 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; in sdma_v6_0_ring_emit_hdp_flush()
320 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v6_0_ring_emit_hdp_flush()
321 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v6_0_ring_emit_hdp_flush()
H A Dsdma_v5_2.c300 u32 ref_and_mask = 0; in sdma_v5_2_ring_emit_hdp_flush() local
306 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; in sdma_v5_2_ring_emit_hdp_flush()
313 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v5_2_ring_emit_hdp_flush()
314 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v5_2_ring_emit_hdp_flush()
H A Dsdma_v4_4_2.c365 u32 ref_and_mask = 0; in sdma_v4_4_2_ring_emit_hdp_flush() local
368 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 in sdma_v4_4_2_ring_emit_hdp_flush()
374 ref_and_mask, ref_and_mask, 10); in sdma_v4_4_2_ring_emit_hdp_flush()
H A Dsdma_v4_0.c814 u32 ref_and_mask = 0; in sdma_v4_0_ring_emit_hdp_flush() local
817 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; in sdma_v4_0_ring_emit_hdp_flush()
822 ref_and_mask, ref_and_mask, 10); in sdma_v4_0_ring_emit_hdp_flush()
H A Dgfx_v7_0.c2064 u32 ref_and_mask; in gfx_v7_0_ring_emit_hdp_flush() local
2070 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; in gfx_v7_0_ring_emit_hdp_flush()
2073 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; in gfx_v7_0_ring_emit_hdp_flush()
2079 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; in gfx_v7_0_ring_emit_hdp_flush()
2088 amdgpu_ring_write(ring, ref_and_mask); in gfx_v7_0_ring_emit_hdp_flush()
2089 amdgpu_ring_write(ring, ref_and_mask); in gfx_v7_0_ring_emit_hdp_flush()
H A Dgfx_v9_4_3.c2481 u32 ref_and_mask, reg_mem_engine; in gfx_v9_4_3_ring_emit_hdp_flush() local
2487 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; in gfx_v9_4_3_ring_emit_hdp_flush()
2490 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; in gfx_v9_4_3_ring_emit_hdp_flush()
2497 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; in gfx_v9_4_3_ring_emit_hdp_flush()
2504 ref_and_mask, ref_and_mask, 0x20); in gfx_v9_4_3_ring_emit_hdp_flush()
H A Dgfx_v11_0.c5253 u32 ref_and_mask, reg_mem_engine; in gfx_v11_0_ring_emit_hdp_flush() local
5259 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; in gfx_v11_0_ring_emit_hdp_flush()
5262 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; in gfx_v11_0_ring_emit_hdp_flush()
5269 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; in gfx_v11_0_ring_emit_hdp_flush()
5276 ref_and_mask, ref_and_mask, 0x20); in gfx_v11_0_ring_emit_hdp_flush()
H A Dgfx_v8_0.c6043 u32 ref_and_mask, reg_mem_engine; in gfx_v8_0_ring_emit_hdp_flush() local
6049 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; in gfx_v8_0_ring_emit_hdp_flush()
6052 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; in gfx_v8_0_ring_emit_hdp_flush()
6059 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; in gfx_v8_0_ring_emit_hdp_flush()
6069 amdgpu_ring_write(ring, ref_and_mask); in gfx_v8_0_ring_emit_hdp_flush()
6070 amdgpu_ring_write(ring, ref_and_mask); in gfx_v8_0_ring_emit_hdp_flush()
H A Dgfx_v9_0.c5113 u32 ref_and_mask, reg_mem_engine; in gfx_v9_0_ring_emit_hdp_flush() local
5119 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; in gfx_v9_0_ring_emit_hdp_flush()
5122 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; in gfx_v9_0_ring_emit_hdp_flush()
5129 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; in gfx_v9_0_ring_emit_hdp_flush()
5136 ref_and_mask, ref_and_mask, 0x20); in gfx_v9_0_ring_emit_hdp_flush()
H A Dgfx_v10_0.c8257 u32 ref_and_mask, reg_mem_engine; in gfx_v10_0_ring_emit_hdp_flush() local
8263 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; in gfx_v10_0_ring_emit_hdp_flush()
8266 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; in gfx_v10_0_ring_emit_hdp_flush()
8273 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; in gfx_v10_0_ring_emit_hdp_flush()
8280 ref_and_mask, ref_and_mask, 0x20); in gfx_v10_0_ring_emit_hdp_flush()
/openbsd/sys/dev/pci/drm/radeon/
H A Dcik_sdma.c174 u32 ref_and_mask; in cik_sdma_hdp_flush_ring_emit() local
177 ref_and_mask = SDMA0; in cik_sdma_hdp_flush_ring_emit()
179 ref_and_mask = SDMA1; in cik_sdma_hdp_flush_ring_emit()
184 radeon_ring_write(ring, ref_and_mask); /* reference */ in cik_sdma_hdp_flush_ring_emit()
185 radeon_ring_write(ring, ref_and_mask); /* mask */ in cik_sdma_hdp_flush_ring_emit()
H A Dcik.c3498 u32 ref_and_mask; in cik_hdp_flush_cp_ring_emit() local
3506 ref_and_mask = CP2 << ring->pipe; in cik_hdp_flush_cp_ring_emit()
3509 ref_and_mask = CP6 << ring->pipe; in cik_hdp_flush_cp_ring_emit()
3516 ref_and_mask = CP0; in cik_hdp_flush_cp_ring_emit()
3526 radeon_ring_write(ring, ref_and_mask); in cik_hdp_flush_cp_ring_emit()
3527 radeon_ring_write(ring, ref_and_mask); in cik_hdp_flush_cp_ring_emit()