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Searched refs:reg_offsets (Results 1 – 10 of 10) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/display/dc/dce100/
H A Ddce100_hw_sequencer.c43 static const struct dce100_hw_seq_reg_offsets reg_offsets[] = { variable
65 (reg + reg_offsets[id].crtc)
/openbsd/sys/dev/pci/drm/amd/display/dc/dce112/
H A Ddce112_hw_sequencer.c42 static const struct dce112_hw_seq_reg_offsets reg_offsets[] = { variable
63 (reg + reg_offsets[id].crtc)
H A Ddce112_compressor.c43 static const struct dce112_compressor_reg_offsets reg_offsets[] = { variable
402 cp110->offsets = reg_offsets[params->inst]; in dce112_compressor_enable_fbc()
/openbsd/sys/dev/pci/drm/amd/display/dc/dce120/
H A Ddce120_hw_sequencer.c54 static const struct dce120_hw_seq_reg_offsets reg_offsets[] = {
76 (reg + reg_offsets[id].crtc)
/openbsd/sys/dev/pci/drm/amd/display/dc/dce80/
H A Ddce80_timing_generator.c51 static const struct dce110_timing_generator_offsets reg_offsets[] = { variable
234 tg110->derived_offsets = reg_offsets[instance]; in dce80_timing_generator_construct()
/openbsd/sys/dev/pci/drm/amd/display/dc/dce60/
H A Ddce60_timing_generator.c51 static const struct dce110_timing_generator_offsets reg_offsets[] = { variable
252 tg110->derived_offsets = reg_offsets[instance]; in dce60_timing_generator_construct()
/openbsd/sys/dev/pci/drm/amd/display/dc/dce110/
H A Ddce110_compressor.c44 static const struct dce110_compressor_reg_offsets reg_offsets[] = { variable
78 cp110->offsets = reg_offsets[crtc_inst]; in reset_lb_on_vblank()
304 cp110->offsets = reg_offsets[params->inst]; in dce110_compressor_program_compressed_surface_address_and_pitch()
H A Ddce110_hw_sequencer.c98 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = { variable
114 (reg + reg_offsets[id].blnd)
117 (reg + reg_offsets[id].crtc)
/openbsd/sys/dev/pci/drm/i915/gt/
H A Dintel_lrc.c682 static const u8 *reg_offsets(const struct intel_engine_cs *engine) in reg_offsets() function
947 set_offsets(regs, reg_offsets(engine), engine, inhibit); in __lrc_init_regs()
1491 set_offsets(ce->lrc_reg_state, reg_offsets(engine), engine, false); in lrc_update_offsets()
/openbsd/sys/dev/pci/drm/amd/display/dc/dcn10/
H A Ddcn10_hw_sequencer.c955 inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt; in dcn10_enable_stream_timing()