| /openbsd/sys/dev/pci/drm/radeon/ |
| H A D | rv730_dpm.c | 39 RV770_SMC_SCLK_VALUE *sclk) in rv730_populate_sclk_value() argument
106 sclk->sclk_value = cpu_to_be32(engine_clock); in rv730_populate_sclk_value()
107 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv730_populate_sclk_value()
108 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv730_populate_sclk_value()
306 table->ACPIState.levels[0].sclk.sclk_value = 0; in rv730_populate_smc_acpi_state()
342 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = in rv730_populate_smc_initial_state()
353 table->initialState.levels[0].sclk.sclk_value = in rv730_populate_smc_initial_state()
354 cpu_to_be32(initial_state->low.sclk); in rv730_populate_smc_initial_state()
413 state->high.sclk, in rv730_program_memory_timing_parameters()
423 state->medium.sclk, in rv730_program_memory_timing_parameters()
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| H A D | btc_dpm.c | 2117 ps->high.sclk = max_limits->sclk; in btc_apply_state_adjust_rules()
2126 ps->medium.sclk = max_limits->sclk; in btc_apply_state_adjust_rules()
2134 if (ps->low.sclk > max_limits->sclk) in btc_apply_state_adjust_rules()
2135 ps->low.sclk = max_limits->sclk; in btc_apply_state_adjust_rules()
2145 sclk = ps->low.sclk; in btc_apply_state_adjust_rules()
2150 sclk = ps->low.sclk; in btc_apply_state_adjust_rules()
2157 ps->low.sclk = sclk; in btc_apply_state_adjust_rules()
2166 if (ps->medium.sclk < ps->low.sclk) in btc_apply_state_adjust_rules()
2167 ps->medium.sclk = ps->low.sclk; in btc_apply_state_adjust_rules()
2170 if (ps->high.sclk < ps->medium.sclk) in btc_apply_state_adjust_rules()
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| H A D | rv770_dpm.c | 281 a_n = (int)state->high.sclk * pi->lhp + (int)state->medium.sclk * in rv770_populate_smc_t()
631 &level->sclk); in rv770_convert_power_level_to_smc()
634 &level->sclk); in rv770_convert_power_level_to_smc()
637 &level->sclk); in rv770_convert_power_level_to_smc()
749 if (state->high.sclk < (state->low.sclk * 0xFF / 0x40)) in rv770_program_memory_timing_parameters()
1444 if (new_state->high.sclk >= current_state->high.sclk) in rv770_set_uvd_clock_before_set_eng_clock()
1461 if (new_state->high.sclk < current_state->high.sclk) in rv770_set_uvd_clock_after_set_eng_clock()
2182 u32 sclk, mclk; in rv7xx_parse_pplib_clock_info() local
2218 pl->sclk = sclk; in rv7xx_parse_pplib_clock_info()
2261 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; in rv7xx_parse_pplib_clock_info()
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| H A D | trinity_dpm.c | 1292 if (sclk < 20000) in trinity_calculate_vce_wm()
1322 if (sclk < min) in trinity_get_sleep_divider_id_from_clock()
1523 ps->levels[i].sclk = in trinity_apply_state_adjust_rules()
1529 if (ps->levels[i].sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) in trinity_apply_state_adjust_rules()
1530 ps->levels[i].sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; in trinity_apply_state_adjust_rules()
1670 u32 sclk; in trinity_parse_pplib_clock_info() local
1674 pl->sclk = sclk; in trinity_parse_pplib_clock_info()
1764 u32 sclk; in trinity_parse_power_table() local
1770 rdev->pm.dpm.vce_states[i].sclk = sclk; in trinity_parse_power_table()
1981 i, pl->sclk, in trinity_dpm_print_power_state()
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| H A D | kv_dpm.c | 1771 table->sclk = in kv_construct_max_power_limits_table()
1886 if (sclk < min) in kv_get_sleep_divider_id_from_clock()
1986 if (ps->levels[i].sclk < sclk) in kv_apply_state_adjust_rules()
1987 ps->levels[i].sclk = sclk; in kv_apply_state_adjust_rules()
2414 u32 sclk; in kv_parse_pplib_clock_info() local
2418 pl->sclk = sclk; in kv_parse_pplib_clock_info()
2506 u32 sclk; in kv_parse_power_table() local
2512 rdev->pm.dpm.vce_states[i].sclk = sclk; in kv_parse_power_table()
2605 u32 sclk, tmp; in kv_dpm_debugfs_print_current_performance_level() local
2628 u32 sclk; in kv_dpm_get_current_sclk() local
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| H A D | rv740_dpm.c | 120 RV770_SMC_SCLK_VALUE *sclk) in rv740_populate_sclk_value() argument
175 sclk->sclk_value = cpu_to_be32(engine_clock); in rv740_populate_sclk_value()
176 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv740_populate_sclk_value()
177 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv740_populate_sclk_value()
178 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv740_populate_sclk_value()
179 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum); in rv740_populate_sclk_value()
180 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2); in rv740_populate_sclk_value()
385 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv740_populate_smc_acpi_state()
386 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv740_populate_smc_acpi_state()
387 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv740_populate_smc_acpi_state()
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| H A D | ni_dpm.c | 810 if (ps->performance_levels[i].sclk > max_limits->sclk) in ni_apply_state_adjust_rules()
811 ps->performance_levels[i].sclk = max_limits->sclk; in ni_apply_state_adjust_rules()
834 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) in ni_apply_state_adjust_rules()
835 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; in ni_apply_state_adjust_rules()
2058 sclk->sclk_value = engine_clock; in ni_calculate_sclk_params()
2071 NISLANDS_SMC_SCLK_VALUE *sclk) in ni_populate_sclk_value() argument
2100 u32 sclk = 0; in ni_init_smc_spll_table() local
2148 sclk += 512; in ni_init_smc_spll_table()
2328 ret = ni_populate_sclk_value(rdev, pl->sclk, &level->sclk); in ni_convert_power_level_to_smc()
3981 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; in ni_parse_pplib_clock_info()
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| H A D | sumo_dpm.c | 790 pi->acpi_pl.sclk, in sumo_program_acpi_power_level()
1004 u32 sclk, in sumo_get_sleep_divider_id_from_clock() argument
1013 if (sclk < min) in sumo_get_sleep_divider_id_from_clock()
1116 ps->levels[i].sclk = in sumo_apply_state_adjust_rules()
1436 u32 sclk; in sumo_parse_pplib_clock_info() local
1440 pl->sclk = sclk; in sumo_parse_pplib_clock_info()
1808 i, pl->sclk, in sumo_dpm_print_power_state()
1829 current_index, pl->sclk, in sumo_dpm_debugfs_print_current_performance_level()
1837 current_index, pl->sclk, in sumo_dpm_debugfs_print_current_performance_level()
1854 return pl->sclk; in sumo_dpm_get_current_sclk()
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| H A D | si_dpm.c | 2833 u32 sclk = 0; in si_init_smc_spll_table() local
3019 if (ps->performance_levels[i].sclk > max_limits->sclk) in si_apply_state_adjust_rules()
3020 ps->performance_levels[i].sclk = max_limits->sclk; in si_apply_state_adjust_rules()
3073 sclk = ps->performance_levels[0].sclk; in si_apply_state_adjust_rules()
3085 ps->performance_levels[0].sclk = sclk; in si_apply_state_adjust_rules()
3091 sclk = ps->performance_levels[0].sclk; in si_apply_state_adjust_rules()
3093 if (sclk < ps->performance_levels[i].sclk) in si_apply_state_adjust_rules()
3094 sclk = ps->performance_levels[i].sclk; in si_apply_state_adjust_rules()
3097 ps->performance_levels[i].sclk = sclk; in si_apply_state_adjust_rules()
4197 (sclk <= limits->entries[i].sclk) && in si_populate_phase_shedding_value()
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| H A D | rv6xx_dpm.c | 439 state->low.sclk; in rv6xx_calculate_engine_speed_stepping_parameters()
441 state->medium.sclk; in rv6xx_calculate_engine_speed_stepping_parameters()
443 state->high.sclk; in rv6xx_calculate_engine_speed_stepping_parameters()
1028 state->medium.sclk, in rv6xx_calculate_ap()
1036 state->high.sclk, in rv6xx_calculate_ap()
1439 new_state->low.sclk, in rv6xx_generate_low_step()
1522 if (new_state->high.sclk >= current_state->high.sclk) in rv6xx_set_uvd_clock_before_set_eng_clock()
1539 if (new_state->high.sclk < current_state->high.sclk) in rv6xx_set_uvd_clock_after_set_eng_clock()
1821 u32 sclk, mclk; in rv6xx_parse_pplib_clock_info() local
1844 pl->sclk = sclk; in rv6xx_parse_pplib_clock_info()
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| H A D | rs690.c | 269 fixed20_12 sclk; member
281 fixed20_12 sclk, core_bandwidth, max_bandwidth; in rs690_crtc_bandwidth_compute() local
298 sclk.full = dfixed_const(selected_sclk); in rs690_crtc_bandwidth_compute()
299 sclk.full = dfixed_div(sclk, a); in rs690_crtc_bandwidth_compute()
303 core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); in rs690_crtc_bandwidth_compute()
387 sclk.full = dfixed_mul(max_bandwidth, a); in rs690_crtc_bandwidth_compute()
389 sclk.full = dfixed_div(a, sclk); in rs690_crtc_bandwidth_compute()
396 chunk_time.full = dfixed_mul(sclk, a); in rs690_crtc_bandwidth_compute()
484 fill_rate.full = dfixed_div(wm0->sclk, a); in rs690_compute_mode_priority()
532 fill_rate.full = dfixed_div(wm0->sclk, a); in rs690_compute_mode_priority()
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| H A D | ci_dpm.c | 777 u32 sclk, mclk; in ci_apply_state_adjust_rules() local
808 if (ps->performance_levels[i].sclk > max_limits->sclk) in ci_apply_state_adjust_rules()
809 ps->performance_levels[i].sclk = max_limits->sclk; in ci_apply_state_adjust_rules()
817 sclk = ps->performance_levels[0].sclk; in ci_apply_state_adjust_rules()
820 sclk = ps->performance_levels[0].sclk; in ci_apply_state_adjust_rules()
825 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; in ci_apply_state_adjust_rules()
830 ps->performance_levels[0].sclk = sclk; in ci_apply_state_adjust_rules()
2350 if (sclk < limits->entries[i].sclk) { in ci_populate_phase_value_based_on_sclk()
2484 u32 sclk, in ci_populate_memory_timing_parameters() argument
5593 rdev->pm.dpm.vce_states[i].sclk = sclk; in ci_parse_power_table()
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| H A D | rs780_dpm.c | 752 u32 sclk; in rs780_parse_pplib_clock_info() local
754 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow); in rs780_parse_pplib_clock_info()
755 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16; in rs780_parse_pplib_clock_info()
756 ps->sclk_low = sclk; in rs780_parse_pplib_clock_info()
757 sclk = le16_to_cpu(clock_info->rs780.usHighEngineClockLow); in rs780_parse_pplib_clock_info()
758 sclk |= clock_info->rs780.ucHighEngineClockHigh << 16; in rs780_parse_pplib_clock_info()
759 ps->sclk_high = sclk; in rs780_parse_pplib_clock_info()
991 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) / in rs780_dpm_debugfs_print_current_performance_level() local
997 if (sclk < (ps->sclk_low + 500)) in rs780_dpm_debugfs_print_current_performance_level()
1013 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) / in rs780_dpm_get_current_sclk() local
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| H A D | radeon_atombios.c | 2488 u32 sclk, mclk; in radeon_atombios_parse_pplib_clock_info() local
2494 sclk |= clock_info->sumo.ucEngineClockHigh << 16; in radeon_atombios_parse_pplib_clock_info()
2495 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; in radeon_atombios_parse_pplib_clock_info()
2499 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; in radeon_atombios_parse_pplib_clock_info()
2503 sclk |= clock_info->ci.ucEngineClockHigh << 16; in radeon_atombios_parse_pplib_clock_info()
2507 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; in radeon_atombios_parse_pplib_clock_info()
2512 sclk |= clock_info->si.ucEngineClockHigh << 16; in radeon_atombios_parse_pplib_clock_info()
2516 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; in radeon_atombios_parse_pplib_clock_info()
2529 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; in radeon_atombios_parse_pplib_clock_info()
2538 sclk |= clock_info->r600.ucEngineClockHigh << 16; in radeon_atombios_parse_pplib_clock_info()
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| H A D | cypress_dpm.c | 694 ret = rv740_populate_sclk_value(rdev, pl->sclk, &level->sclk); in cypress_convert_power_level_to_smc()
728 pl->sclk, in cypress_convert_power_level_to_smc()
735 pl->sclk, in cypress_convert_power_level_to_smc()
936 new_state->low.sclk, in cypress_program_memory_timing_parameters()
939 new_state->medium.sclk, in cypress_program_memory_timing_parameters()
942 new_state->high.sclk, in cypress_program_memory_timing_parameters()
1278 table->initialState.levels[0].sclk.sclk_value = in cypress_populate_smc_initial_state()
1279 cpu_to_be32(initial_state->low.sclk); in cypress_populate_smc_initial_state()
1450 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = in cypress_populate_smc_acpi_state()
1452 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = in cypress_populate_smc_acpi_state()
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| H A D | rv770_dpm.h | 143 u32 sclk; member
182 RV770_SMC_SCLK_VALUE *sclk);
203 RV770_SMC_SCLK_VALUE *sclk);
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| H A D | radeon_pm.c | 174 u32 sclk, mclk; in radeon_set_power_state() local
184 if (sclk > rdev->pm.default_sclk) in radeon_set_power_state()
185 sclk = rdev->pm.default_sclk; in radeon_set_power_state()
206 if (sclk < rdev->pm.current_sclk) in radeon_set_power_state()
223 if (sclk != rdev->pm.current_sclk) { in radeon_set_power_state()
225 radeon_set_engine_clock(rdev, sclk); in radeon_set_power_state()
227 rdev->pm.current_sclk = sclk; in radeon_set_power_state()
344 clock_info->sclk * 10); in radeon_pm_print_states()
348 clock_info->sclk * 10, in radeon_pm_print_states()
731 u32 sclk = 0; in radeon_hwmon_show_sclk() local
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| H A D | sumo_dpm.h | 33 u32 sclk; member
208 u32 sclk,
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| H A D | radeon_clocks.c | 47 uint32_t fb_div, ref_div, post_div, sclk; in radeon_legacy_get_engine_clock() local
60 sclk = fb_div / ref_div; in radeon_legacy_get_engine_clock()
64 sclk >>= 1; in radeon_legacy_get_engine_clock()
66 sclk >>= 2; in radeon_legacy_get_engine_clock()
68 sclk >>= 3; in radeon_legacy_get_engine_clock()
70 return sclk; in radeon_legacy_get_engine_clock()
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| H A D | rv515.c | 920 fixed20_12 sclk; member
932 fixed20_12 sclk; in rv515_crtc_bandwidth_compute() local
950 sclk.full = dfixed_const(selected_sclk); in rv515_crtc_bandwidth_compute()
951 sclk.full = dfixed_div(sclk, a); in rv515_crtc_bandwidth_compute()
1018 chunk_time.full = dfixed_div(a, sclk); in rv515_crtc_bandwidth_compute()
1103 fill_rate.full = dfixed_div(wm0->sclk, a); in rv515_compute_mode_priority()
1151 fill_rate.full = dfixed_div(wm0->sclk, a); in rv515_compute_mode_priority()
1178 fill_rate.full = dfixed_div(wm1->sclk, a); in rv515_compute_mode_priority()
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| /openbsd/sys/dev/pci/drm/amd/pm/legacy-dpm/ |
| H A D | amdgpu_kv_dpm.c | 2031 table->sclk = in kv_construct_max_power_limits_table()
2145 if (sclk < min) in kv_get_sleep_divider_id_from_clock()
2245 if (ps->levels[i].sclk < sclk) in kv_apply_state_adjust_rules()
2246 ps->levels[i].sclk = sclk; in kv_apply_state_adjust_rules()
2676 u32 sclk; in kv_parse_pplib_clock_info() local
2680 pl->sclk = sclk; in kv_parse_pplib_clock_info()
2766 u32 sclk; in kv_parse_power_table() local
2772 adev->pm.dpm.vce_states[i].sclk = sclk; in kv_parse_power_table()
2861 u32 sclk, tmp; in kv_dpm_debugfs_print_current_performance_level() local
3205 return ((kv_cpl1->sclk == kv_cpl2->sclk) && in kv_are_power_levels_equal()
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| H A D | amdgpu_si_dpm.c | 3493 ps->performance_levels[i].sclk = max_limits->sclk; in si_apply_state_adjust_rules()
3546 sclk = ps->performance_levels[0].sclk; in si_apply_state_adjust_rules()
3558 ps->performance_levels[0].sclk = sclk; in si_apply_state_adjust_rules()
3564 sclk = ps->performance_levels[0].sclk; in si_apply_state_adjust_rules()
3566 if (sclk < ps->performance_levels[i].sclk) in si_apply_state_adjust_rules()
3567 sclk = ps->performance_levels[i].sclk; in si_apply_state_adjust_rules()
3570 ps->performance_levels[i].sclk = sclk; in si_apply_state_adjust_rules()
4674 (sclk <= limits->entries[i].sclk) && in si_populate_phase_shedding_value()
7343 adev->pm.dpm.vce_states[i].sclk = sclk; in si_parse_power_table()
7956 (si_cpl1->sclk == si_cpl2->sclk) && in si_are_power_levels_equal()
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| /openbsd/sys/dev/pci/drm/amd/pm/swsmu/smu11/ |
| H A D | cyan_skillfish_ppt.c | 57 uint32_t sclk; member
466 cyan_skillfish_user_settings.sclk = input[1]; in cyan_skillfish_od_edit_dpm_table()
476 cyan_skillfish_user_settings.sclk = cyan_skillfish_sclk_default; in cyan_skillfish_od_edit_dpm_table()
486 if (cyan_skillfish_user_settings.sclk < CYAN_SKILLFISH_SCLK_MIN || in cyan_skillfish_od_edit_dpm_table()
487 cyan_skillfish_user_settings.sclk > CYAN_SKILLFISH_SCLK_MAX) { in cyan_skillfish_od_edit_dpm_table()
502 cyan_skillfish_user_settings.sclk, NULL); in cyan_skillfish_od_edit_dpm_table()
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| /openbsd/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ |
| H A D | ppatomctrl.h | 294 …oltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t sclk, uint16_t virtual_v…
320 uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage, uint16_t dpm_level, bool debug);
325 uint32_t sclk, uint16_t virtual_voltage_Id, uint32_t *voltage);
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dml/calcs/ |
| H A D | dce_calcs.c | 102 struct bw_fixed *sclk; in calculate_bandwidth() local
129 sclk = kcalloc(8, sizeof(*sclk), GFP_KERNEL); in calculate_bandwidth()
130 if (!sclk) in calculate_bandwidth()
144 sclk[s_low] = vbios->low_sclk; in calculate_bandwidth()
145 sclk[s_mid1] = vbios->mid1_sclk; in calculate_bandwidth()
146 sclk[s_mid2] = vbios->mid2_sclk; in calculate_bandwidth()
147 sclk[s_mid3] = vbios->mid3_sclk; in calculate_bandwidth()
148 sclk[s_mid4] = vbios->mid4_sclk; in calculate_bandwidth()
149 sclk[s_mid5] = vbios->mid5_sclk; in calculate_bandwidth()
150 sclk[s_mid6] = vbios->mid6_sclk; in calculate_bandwidth()
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