/openbsd/gnu/usr.bin/binutils/cpu/ |
H A D | iq2000.cpu | 367 (dnop shamt "shift amount" () h-uint f-shamt) 593 (set rd (ror rt shamt)) 599 "sll $rd,$rt,$shamt" 601 (set rd (sll rt shamt)) 623 "slmv $rd,$rt,$rs,$shamt" 693 "sra ${rd-rt},$shamt" 699 "sra $rd,$rt,$shamt" 701 (set rd (sra rt shamt)) 717 "srl $rd,$rt,$shamt" 719 (set rd (srl rt shamt)) [all …]
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H A D | iq2000m.cpu | 211 (+ OP_COP3 (f-rs 9) rt rd (f-shamt 0) (f-func 0)) 247 (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 3)) 253 (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 7)) 271 (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 8)) 283 (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 2)) 289 (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 6)) 307 (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 1)) 313 (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 5)) 373 (+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 7)) 391 (+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 4)) [all …]
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H A D | iq10.cpu | 293 (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_CRC32) 350 (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_DBD) 372 (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_RBA) 378 (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_RBAL) 384 (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_RBAR) 390 (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_WBA) 396 (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_WBAU) 402 (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_WBAC) 468 (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_PKRLA) 518 (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_SWWR) [all …]
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/openbsd/gnu/usr.bin/binutils-2.17/cpu/ |
H A D | iq2000.cpu | 350 (dnop shamt "shift amount" () h-uint f-shamt) 576 (set rd (ror rt shamt)) 582 "sll $rd,$rt,$shamt" 584 (set rd (sll rt shamt)) 606 "slmv $rd,$rt,$rs,$shamt" 676 "sra ${rd-rt},$shamt" 682 "sra $rd,$rt,$shamt" 684 (set rd (sra rt shamt)) 700 "srl $rd,$rt,$shamt" 702 (set rd (srl rt shamt)) [all …]
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H A D | iq2000m.cpu | 211 (+ OP_COP3 (f-rs 9) rt rd (f-shamt 0) (f-func 0)) 247 (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 3)) 253 (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 7)) 271 (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 8)) 283 (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 2)) 289 (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 6)) 307 (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 1)) 313 (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 5)) 373 (+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 7)) 391 (+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 4)) [all …]
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H A D | iq10.cpu | 293 (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_CRC32) 350 (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_DBD) 372 (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_RBA) 378 (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_RBAL) 384 (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_RBAR) 390 (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_WBA) 396 (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_WBAU) 402 (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_WBAC) 468 (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_PKRLA) 518 (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_SWWR) [all …]
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H A D | sh64-compact.cpu | 1462 (sequence ((QI shamt)) 1463 (set shamt (and QI rm 31)) 1465 (set rn (sll rn shamt)) 1466 (if (ne shamt 0) 1467 (set rn (sra rn (sub 32 shamt))) 1494 (sequence ((QI shamt)) 1495 (set shamt (and QI rm 31)) 1497 (set rn (sll rn shamt)) 1498 (if (ne shamt 0) 1499 (set rn (srl rn (sub 32 shamt)))
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/openbsd/gnu/llvm/lldb/source/Plugins/Instruction/RISCV/ |
H A D | RISCVCInstructions.h | 230 uint16_t shamt = ((inst >> 7) & 0x20) | ((inst >> 2) & 0x1f); in DecodeC_SLLI() local 231 if (rd == 0 || shamt == 0) in DecodeC_SLLI() 233 return SLLI{rd, rd, uint8_t(shamt)}; in DecodeC_SLLI() 238 uint16_t shamt = ((inst >> 7) & 0x20) | ((inst >> 2) & 0x1f); in DecodeC_SRLI() local 239 if (shamt == 0) in DecodeC_SRLI() 241 return SRLI{rd, rd, uint8_t(shamt)}; in DecodeC_SRLI() 246 uint16_t shamt = ((inst >> 7) & 0x20) | ((inst >> 2) & 0x1f); in DecodeC_SRAI() local 247 if (shamt == 0) in DecodeC_SRAI() 249 return SRAI{rd, rd, uint8_t(shamt)}; in DecodeC_SRAI()
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H A D | EmulateInstructionRISCV.cpp | 865 return inst.rd.Write(m_emu, rs1 << inst.shamt); in operator ()() 872 return inst.rd.Write(m_emu, rs1 >> inst.shamt); in operator ()() 879 return inst.rd.Write(m_emu, rs1 >> inst.shamt); in operator ()() 895 SextW(rs1 << inst.shamt)); in operator ()() 903 SextW(rs1 >> inst.shamt)); in operator ()() 911 SextW(rs1 >> inst.shamt)); in operator ()()
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H A D | RISCVInstructions.h | 76 uint32_t shamt; \
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/openbsd/gnu/llvm/llvm/lib/Target/RISCV/ |
H A D | RISCVInstrInfoZb.td | 284 "$rd, $rs1, $shamt">; 291 "$rd, $rs1, $shamt">; 299 "$rd, $rs1, $shamt">; 500 def : InstAlias<"ror $rd, $rs1, $shamt", 505 def : InstAlias<"rorw $rd, $rs1, $shamt", 510 def : InstAlias<"bset $rd, $rs1, $shamt", 512 def : InstAlias<"bclr $rd, $rs1, $shamt", 514 def : InstAlias<"binv $rd, $rs1, $shamt", 516 def : InstAlias<"bext $rd, $rs1, $shamt", 537 def : Pat<(rotl GPR:$rs1, uimmlog2xlen:$shamt), [all …]
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H A D | RISCVInstrInfo.td | 546 "$rd, $rs1, $shamt">, 574 "$rd, $rs1, $shamt">, 1041 def : InstAlias<"sll $rd, $rs1, $shamt", 1043 def : InstAlias<"srl $rd, $rs1, $shamt", 1045 def : InstAlias<"sra $rd, $rs1, $shamt", 1057 def : InstAlias<"sllw $rd, $rs1, $shamt", 1059 def : InstAlias<"srlw $rd, $rs1, $shamt", 1061 def : InstAlias<"sraw $rd, $rs1, $shamt", 1759 (SRLIW GPR:$rs1, uimm5:$shamt)>; 1763 (SRAIW GPR:$rs1, uimm5:$shamt)>; [all …]
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H A D | RISCVInstrFormats.td | 364 bits<6> shamt; 370 let Inst{25-20} = shamt; 380 bits<5> shamt; 385 let Inst{24-20} = shamt;
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/openbsd/sys/arch/mips64/include/ |
H A D | mips_opcode.h | 69 unsigned shamt: 5; member 108 unsigned shamt: 5; member
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/openbsd/gnu/llvm/llvm/lib/Target/X86/ |
H A D | X86InstrShiftRotate.td | 872 // Convert a ROTL shamt to a ROTR shamt on 32-bit integer. 877 // Convert a ROTL shamt to a ROTR shamt on 64-bit integer. 926 def : Pat<(rotr GR32:$src, (i8 imm:$shamt)), 927 (RORX32ri GR32:$src, imm:$shamt)>; 928 def : Pat<(rotr GR64:$src, (i8 imm:$shamt)), 929 (RORX64ri GR64:$src, imm:$shamt)>; 931 def : Pat<(rotl GR32:$src, (i8 imm:$shamt)), 933 def : Pat<(rotl GR64:$src, (i8 imm:$shamt)), 937 def : Pat<(rotr (loadi32 addr:$src), (i8 imm:$shamt)), 938 (RORX32mi addr:$src, imm:$shamt)>; [all …]
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/openbsd/sys/arch/mips64/mips64/ |
H A D | db_disasm.c | 600 if (i.RType.shamt != 0) in dbmd_print_insn() 604 if (i.RType.shamt != 0) in dbmd_print_insn() 608 if (i.RType.shamt != 0) in dbmd_print_insn() 616 if (i.RType.shamt != 0) in dbmd_print_insn() 637 i.RType.shamt); in dbmd_print_insn()
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H A D | trap.c | 685 inst.RType.shamt == 0 && in itsa()
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H A D | fp_emulate.c | 1846 if ((inst.RType.rt & 0x02) != 0 || inst.RType.shamt != 0) in nofpu_emulate_movci()
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/openbsd/gnu/llvm/llvm/lib/Target/Mips/ |
H A D | MipsInstrFormats.td | 18 // shamt - only used on shift instructions, contains the shift amount. 148 // Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|> 158 bits<5> shamt; 167 let Inst{10-6} = shamt; 247 bits<5> shamt; 256 let Inst{10-6} = shamt;
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H A D | MicroMipsInstrFormats.td | 98 bits<3> shamt; 105 let Inst{3-1} = shamt; 365 bits<5> shamt; 372 let Inst{15-11} = shamt;
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H A D | MicroMipsInstrInfo.td | 336 MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt), 337 !strconcat(opstr, "\t$rd, $rt, $shamt"), [], Itin, FrmR>; 793 (rotr GPR32Opnd:$rt, immZExt5:$shamt))]; 1380 def : MipsInstAlias<"sll $rd, $shamt", 1381 (SLL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>; 1382 def : MipsInstAlias<"sra $rd, $shamt", 1383 (SRA_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>; 1384 def : MipsInstAlias<"srl $rd, $shamt", 1385 (SRL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
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H A D | MicroMips32r6InstrFormats.td | 530 bits<5> shamt; 537 let Inst{15-11} = shamt;
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H A D | MipsDSPInstrInfo.td | 1372 DSPPat<(Node ValTy:$a, Imm:$shamt), (Inst ValTy:$a, Imm:$shamt), Pred>;
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H A D | Mips64InstrInfo.td | 17 // shamt must fit in 6 bits. 414 let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
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H A D | MipsInstrInfo.td | 1251 // shamt field must fit in 5 bits. 1363 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt), 1364 !strconcat(opstr, "\t$rd, $rt, $shamt"), 1365 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
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