Searched refs:LOAD (Results 1 – 12 of 12) sorted by relevance
/qemu/target/s390x/tcg/ |
H A D | insn-data.h.inc | 416 /* LOAD */ 437 /* LOAD ADDRESS */ 445 /* LOAD AND ADD */ 451 /* LOAD AND AND */ 457 /* LOAD AND OR */ 478 /* LOAD BYTE */ 509 /* LOAD HIGH */ 593 /* LOAD ZERO */ 598 /* LOAD FPC */ 1030 /* VECTOR LOAD */ [all …]
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/qemu/linux-user/ |
H A D | gen-vdso-elfn.c.inc | 146 fprintf(stderr, "Multiple LOAD segments\n"); 150 fprintf(stderr, "LOAD segment does not cover EHDR\n"); 154 fprintf(stderr, "LOAD segment not loaded at address 0\n"); 159 fprintf(stderr, "LOAD segment does not cover PHDRs\n"); 163 fprintf(stderr, "LOAD segment is not read-write\n"); 186 fprintf(stderr, "LOAD segment does not cover %s\n", which);
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/qemu/docs/devel/ |
H A D | atomics.rst | 125 components of the system, before all the LOAD or STORE operations 129 components of the system, after all the LOAD or STORE operations 143 - ``qatomic_load_acquire()``, which guarantees the LOAD to appear to 145 before all the LOAD or STORE operations specified afterwards. 151 after all the LOAD or STORE operations specified before. 162 - ``smp_rmb()`` guarantees that all the LOAD operations specified before 163 the barrier will appear to happen before all the LOAD operations 184 the barrier will appear to happen after all the LOAD or STORE operations 188 - ``smp_mb()`` guarantees that all the LOAD and STORE operations specified 189 before the barrier will appear to happen before all the LOAD and [all …]
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/qemu/linux-user/arm/nwfpe/ |
H A D | fpopcode.h | 222 #define LOAD(opcode) ((opcode & BIT_LOAD) != 0) macro
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/qemu/target/hexagon/idef-parser/ |
H A D | idef-parser.y | 55 %token ZXT CONSTEXT LOCNT BREV SIGN LOAD STORE PC LPCFG 339 | LOAD '(' IMM ',' IMM ',' SIGN ',' var ',' lvalue ')'
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/qemu/target/hexagon/ |
H A D | attribs_def.h.inc | 39 DEF_ATTRIB(LOAD, "Loads from memory", "", "")
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H A D | gen_tcg.h | 110 #define fGEN_TCG_LOAD_pcr(SHIFT, LOAD) \ argument 116 LOAD; \
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/qemu/include/hw/misc/ |
H A D | bcm2835_cprman_internals.h | 312 .cm_load_mask = R_CM_ ## pll_ ## _ ## LOAD ## channel_ ## _MASK, \
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/qemu/hw/nvram/ |
H A D | xlnx-versal-efuse-ctrl.c | 145 FIELD(EFUSE_CACHE_LOAD, LOAD, 0, 1)
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H A D | xlnx-zynqmp-efuse.c | 102 FIELD(EFUSE_CACHE_LOAD, LOAD, 0, 1)
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/qemu/target/hexagon/imported/ |
H A D | encode_pp.def | 289 /* LOAD */
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/qemu/tcg/s390x/ |
H A D | tcg-target.c.inc | 429 /* Condition codes that result from a LOAD AND TEST. Here, we have no
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