/qemu/target/arm/tcg/ |
H A D | mte_helper.c | 191 tag_access == MMU_DATA_STORE, attrs); in allocation_tag_mem_probe() 211 if (tag_access == MMU_DATA_STORE) { in allocation_tag_mem_probe() 355 MMU_DATA_STORE, ra); in do_stg() 397 mem1 = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE, in do_st2g() 398 TAG_GRANULE, MMU_DATA_STORE, ra); in do_st2g() 400 MMU_DATA_STORE, TAG_GRANULE, in do_st2g() 401 MMU_DATA_STORE, ra); in do_st2g() 412 mem1 = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE, in do_st2g() 519 tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE, in HELPER() 576 MMU_DATA_STORE, ra); in HELPER() [all …]
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H A D | tlb_helper.c | 204 access_type == MMU_DATA_STORE, fsc); in arm_deliver_fault() 250 same_el, access_type == MMU_DATA_STORE, in arm_deliver_fault() 252 if (access_type == MMU_DATA_STORE in arm_deliver_fault()
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H A D | helper-a64.c | 947 mem = tlb_vaddr_to_host(env, vaddr, MMU_DATA_STORE, mmu_idx); in HELPER() 1108 mem = tlb_vaddr_to_host(env, toaddr, MMU_DATA_STORE, memidx); in set_step() 1146 mem = tlb_vaddr_to_host(env, cleanaddr, MMU_DATA_STORE, memidx); in set_step_tags() 1215 arm_cpu_do_unaligned_access(env_cpu(env), ptr, MMU_DATA_STORE, in check_setg_alignment() 1474 wmem = tlb_vaddr_to_host(env, toaddr, MMU_DATA_STORE, wmemidx); in copy_step() 1546 wmem = tlb_vaddr_to_host(env, toaddr, MMU_DATA_STORE, wmemidx); in copy_step_rev()
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/qemu/target/s390x/ |
H A D | mmu_helper.c | 363 case MMU_DATA_STORE: in mmu_handle_skey() 399 (rw == MMU_DATA_STORE ? FS_WRITE : FS_READ); in mmu_translate() 412 if (is_low_address(vaddr) && rw == MMU_DATA_STORE) { in mmu_translate() 449 if (unlikely(rw == MMU_DATA_STORE && !(*flags & PAGE_WRITE))) { in mmu_translate() 467 if (!mmu_absolute_addr_valid(*raddr, rw == MMU_DATA_STORE)) { in mmu_translate() 594 if (is_low_address(raddr) && rw == MMU_DATA_STORE) { in mmu_translate_real() 603 if (!mmu_absolute_addr_valid(*addr, rw == MMU_DATA_STORE)) { in mmu_translate_real()
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/qemu/target/ppc/ |
H A D | mmu-hash32.c | 179 if (access_type == MMU_DATA_STORE) { in ppc_hash32_direct_store() 199 if (access_type == MMU_DATA_STORE) { in ppc_hash32_direct_store() 219 if (access_type == MMU_DATA_STORE) { in ppc_hash32_direct_store() 370 if (access_type == MMU_DATA_STORE) { in ppc_hash32_xlate() 413 if (access_type == MMU_DATA_STORE) { in ppc_hash32_xlate() 440 if (access_type == MMU_DATA_STORE) { in ppc_hash32_xlate() 458 if (access_type == MMU_DATA_STORE) { in ppc_hash32_xlate()
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H A D | mmu_common.c | 151 if (access_type == MMU_DATA_STORE && ret == 0) { in pte_update_flags() 192 access_type == MMU_DATA_STORE ? 'S' : 'L', in ppc6xx_tlb_check() 382 access_type == MMU_DATA_STORE, type); in mmu6xx_get_physical_address() 440 if ((access_type == MMU_DATA_STORE || ctx->key != 1) && in mmu6xx_get_physical_address() 751 if (access_type == MMU_DATA_STORE) { in ppc_40x_xlate() 762 if (access_type == MMU_DATA_STORE) { in ppc_40x_xlate() 842 if (access_type == MMU_DATA_STORE) { in ppc_6xx_xlate() 863 if (access_type == MMU_DATA_STORE) { in ppc_6xx_xlate() 883 if (access_type == MMU_DATA_STORE) { in ppc_6xx_xlate() 894 if (access_type == MMU_DATA_STORE) { in ppc_6xx_xlate()
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H A D | mmu-radix64.c | 94 case MMU_DATA_STORE: in ppc_radix64_raise_segi() 109 (access_type == MMU_DATA_STORE ? "writing" : "execute"); in access_str() 128 case MMU_DATA_STORE: in ppc_radix64_raise_si() 168 case MMU_DATA_STORE: in ppc_radix64_raise_hsi() 225 case MMU_DATA_STORE: in ppc_radix64_check_rc()
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H A D | user_only_helper.c | 46 if (access_type == MMU_DATA_STORE) { in ppc_cpu_record_sigsegv()
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H A D | mmu-hash64.c | 1001 case MMU_DATA_STORE: in ppc_hash64_xlate() 1039 case MMU_DATA_STORE: in ppc_hash64_xlate() 1073 case MMU_DATA_STORE: in ppc_hash64_xlate() 1115 if (access_type == MMU_DATA_STORE) { in ppc_hash64_xlate() 1134 if (access_type == MMU_DATA_STORE) { in ppc_hash64_xlate()
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H A D | mem_helper.c | 110 MMU_DATA_STORE, mmu_idx, raddr); in helper_stmw() 228 host = probe_contiguous(env, addr, nb, MMU_DATA_STORE, mmu_idx, raddr); in helper_stsw()
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/qemu/include/exec/ |
H A D | mmu-access-type.h | 13 MMU_DATA_STORE = 1, enumerator
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/qemu/accel/tcg/ |
H A D | user-exec.c | 100 return is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; in adjust_signal_pc() 793 case MMU_DATA_STORE: in probe_access_internal() 1070 haddr = cpu_mmu_lookup(cpu, addr, get_memop(oi), ra, MMU_DATA_STORE); in do_st1_mmu() 1082 haddr = cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_STORE); in do_st2_mmu() 1098 haddr = cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_STORE); in do_st4_mmu() 1114 haddr = cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_STORE); in do_st8_mmu() 1130 haddr = cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_STORE); in do_st16_mmu() 1250 cpu_loop_exit_sigbus(cpu, addr, MMU_DATA_STORE, retaddr); in atomic_mmu_lookup()
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H A D | cputlb.c | 109 MMU_DATA_STORE * sizeof(uint64_t)); in tlb_read_idx() 131 return tlb_read_idx(entry, MMU_DATA_STORE); in tlb_addr_write() 1193 MMU_DATA_STORE, prot & PAGE_WRITE); in tlb_set_page_full() 1479 int wp_access = (access_type == MMU_DATA_STORE in probe_access() 1815 cpu_unaligned_access(cpu, addr, MMU_DATA_STORE, in atomic_mmu_lookup() 1834 if (!victim_tlb_hit(cpu, mmu_idx, index, MMU_DATA_STORE, in atomic_mmu_lookup() 1837 MMU_DATA_STORE, mmu_idx, retaddr); in atomic_mmu_lookup() 1880 if (full->slow_flags[MMU_DATA_STORE] & TLB_WATCHPOINT) { in atomic_mmu_lookup() 2488 io_failed(cpu, full, addr, this_size, MMU_DATA_STORE, in int_st_mmio_leN() 2728 crosspage = mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); in do_st1_mmu() [all …]
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/qemu/target/sh4/ |
H A D | helper.c | 369 n = (access_type == MMU_DATA_STORE) in get_mmu_address() 371 } else if ((access_type == MMU_DATA_STORE) && !(matching->pr & 1)) { in get_mmu_address() 373 } else if ((access_type == MMU_DATA_STORE) && !matching->d) { in get_mmu_address() 382 n = (access_type == MMU_DATA_STORE) in get_mmu_address() 406 } else if (access_type == MMU_DATA_STORE) { in get_physical_address()
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/qemu/target/s390x/tcg/ |
H A D | mem_helper.c | 169 (access_type == MMU_DATA_STORE in s390_probe_access() 375 access_prepare(&desta, env, dest, l, MMU_DATA_STORE, mmu_idx, ra); in do_helper_nc() 409 access_prepare(&desta, env, dest, l, MMU_DATA_STORE, mmu_idx, ra); in do_helper_xc() 450 access_prepare(&desta, env, dest, l, MMU_DATA_STORE, mmu_idx, ra); in do_helper_oc() 482 access_prepare(&desta, env, dest, l, MMU_DATA_STORE, mmu_idx, ra); in do_helper_mvc() 522 access_prepare(&desta, env, dest, l, MMU_DATA_STORE, mmu_idx, ra); in HELPER() 543 access_prepare(&desta, env, dest, l, MMU_DATA_STORE, mmu_idx, ra); in HELPER() 924 MMU_DATA_STORE, mmu_idx, ra); in HELPER() 1126 MMU_DATA_STORE, mmu_idx, ra); in HELPER() 1134 MMU_DATA_STORE, mmu_idx, ra); in HELPER() [all …]
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/qemu/target/i386/tcg/user/ |
H A D | excp_helper.c | 40 env->error_code = ((access_type == MMU_DATA_STORE) << PG_ERROR_W_BIT) in x86_cpu_record_sigsegv()
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/qemu/target/alpha/ |
H A D | mem_helper.c | 69 env->trap_arg1 = access_type == MMU_DATA_STORE ? 1 : 0; in alpha_cpu_do_transaction_failed()
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H A D | helper.c | 137 case MMU_DATA_STORE: in alpha_cpu_record_sigsegv() 315 access_type == MMU_DATA_STORE ? 1ull : in alpha_cpu_tlb_fill()
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/qemu/target/microblaze/ |
H A D | helper.c | 85 env->esr |= (access_type == MMU_DATA_STORE) << 10; in mb_cpu_tlb_fill() 89 env->esr |= (access_type == MMU_DATA_STORE) << 10; in mb_cpu_tlb_fill()
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/qemu/target/i386/tcg/sysemu/ |
H A D | excp_helper.c | 69 flags = probe_access_full(inout->env, addr, 0, MMU_DATA_STORE, in ptw_translate() 403 if (access_type == MMU_DATA_STORE) { in mmu_translate() 490 case MMU_DATA_STORE: in mmu_translate()
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/qemu/target/cris/ |
H A D | mmu.c | 160 case MMU_DATA_STORE: in cris_mmu_translate_page() 223 } else if (access_type == MMU_DATA_STORE && cfg_w && !tlb_w) { in cris_mmu_translate_page()
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/qemu/target/riscv/ |
H A D | cpu_helper.c | 1095 updated_pte |= PTE_A | (access_type == MMU_DATA_STORE ? PTE_D : 0); in get_physical_address() 1097 (access_type == MMU_DATA_STORE && !(pte & PTE_D))) { in get_physical_address() 1163 if (access_type != MMU_DATA_STORE && !(pte & PTE_D)) { in get_physical_address() 1197 case MMU_DATA_STORE: in raise_mmu_exception() 1246 if (access_type == MMU_DATA_STORE) { in riscv_cpu_do_transaction_failed() 1273 case MMU_DATA_STORE: in riscv_cpu_do_unaligned_access() 1297 case MMU_DATA_STORE: in pmu_tlb_fill_incr_ctr()
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/qemu/target/openrisc/ |
H A D | mmu.c | 123 : access_type == MMU_DATA_STORE ? PAGE_WRITE in openrisc_cpu_tlb_fill()
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/qemu/target/hppa/ |
H A D | op_helper.c | 52 vaddr = probe_access(env, addr, 3, MMU_DATA_STORE, mmu_idx, ra); in atomic_store_mask32() 79 vaddr = probe_access(env, addr, size, MMU_DATA_STORE, mmu_idx, ra); in atomic_store_mask64()
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/qemu/target/mips/tcg/ |
H A D | op_helper.c | 290 if (access_type == MMU_DATA_STORE) { in mips_cpu_do_unaligned_access()
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