1 /*
2 * SH4 emulation
3 *
4 * Copyright (c) 2005 Samuel Tardieu
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21
22 #include "cpu.h"
23 #include "exec/exec-all.h"
24 #include "exec/page-protection.h"
25 #include "exec/log.h"
26
27 #if !defined(CONFIG_USER_ONLY)
28 #include "hw/sh4/sh_intc.h"
29 #include "sysemu/runstate.h"
30 #endif
31
32 #define MMU_OK 0
33 #define MMU_ITLB_MISS (-1)
34 #define MMU_ITLB_MULTIPLE (-2)
35 #define MMU_ITLB_VIOLATION (-3)
36 #define MMU_DTLB_MISS_READ (-4)
37 #define MMU_DTLB_MISS_WRITE (-5)
38 #define MMU_DTLB_INITIAL_WRITE (-6)
39 #define MMU_DTLB_VIOLATION_READ (-7)
40 #define MMU_DTLB_VIOLATION_WRITE (-8)
41 #define MMU_DTLB_MULTIPLE (-9)
42 #define MMU_DTLB_MISS (-10)
43 #define MMU_IADDR_ERROR (-11)
44 #define MMU_DADDR_ERROR_READ (-12)
45 #define MMU_DADDR_ERROR_WRITE (-13)
46
47 #if defined(CONFIG_USER_ONLY)
48
cpu_sh4_is_cached(CPUSH4State * env,target_ulong addr)49 int cpu_sh4_is_cached(CPUSH4State *env, target_ulong addr)
50 {
51 /* For user mode, only U0 area is cacheable. */
52 return !(addr & 0x80000000);
53 }
54
55 #else /* !CONFIG_USER_ONLY */
56
superh_cpu_do_interrupt(CPUState * cs)57 void superh_cpu_do_interrupt(CPUState *cs)
58 {
59 CPUSH4State *env = cpu_env(cs);
60 int do_irq = cs->interrupt_request & CPU_INTERRUPT_HARD;
61 int do_exp, irq_vector = cs->exception_index;
62
63 /* prioritize exceptions over interrupts */
64
65 do_exp = cs->exception_index != -1;
66 do_irq = do_irq && (cs->exception_index == -1);
67
68 if (env->sr & (1u << SR_BL)) {
69 if (do_exp && cs->exception_index != 0x1e0) {
70 /* In theory a masked exception generates a reset exception,
71 which in turn jumps to the reset vector. However this only
72 works when using a bootloader. When using a kernel and an
73 initrd, they need to be reloaded and the program counter
74 should be loaded with the kernel entry point.
75 qemu_system_reset_request takes care of that. */
76 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
77 return;
78 }
79 if (do_irq && !env->in_sleep) {
80 return; /* masked */
81 }
82 }
83 env->in_sleep = 0;
84
85 if (do_irq) {
86 irq_vector = sh_intc_get_pending_vector(env->intc_handle,
87 (env->sr >> 4) & 0xf);
88 if (irq_vector == -1) {
89 return; /* masked */
90 }
91 }
92
93 if (qemu_loglevel_mask(CPU_LOG_INT)) {
94 const char *expname;
95 switch (cs->exception_index) {
96 case 0x0e0:
97 expname = "addr_error";
98 break;
99 case 0x040:
100 expname = "tlb_miss";
101 break;
102 case 0x0a0:
103 expname = "tlb_violation";
104 break;
105 case 0x180:
106 expname = "illegal_instruction";
107 break;
108 case 0x1a0:
109 expname = "slot_illegal_instruction";
110 break;
111 case 0x800:
112 expname = "fpu_disable";
113 break;
114 case 0x820:
115 expname = "slot_fpu";
116 break;
117 case 0x100:
118 expname = "data_write";
119 break;
120 case 0x060:
121 expname = "dtlb_miss_write";
122 break;
123 case 0x0c0:
124 expname = "dtlb_violation_write";
125 break;
126 case 0x120:
127 expname = "fpu_exception";
128 break;
129 case 0x080:
130 expname = "initial_page_write";
131 break;
132 case 0x160:
133 expname = "trapa";
134 break;
135 default:
136 expname = do_irq ? "interrupt" : "???";
137 break;
138 }
139 qemu_log("exception 0x%03x [%s] raised\n",
140 irq_vector, expname);
141 log_cpu_state(cs, 0);
142 }
143
144 env->ssr = cpu_read_sr(env);
145 env->spc = env->pc;
146 env->sgr = env->gregs[15];
147 env->sr |= (1u << SR_BL) | (1u << SR_MD) | (1u << SR_RB);
148 env->lock_addr = -1;
149
150 if (env->flags & TB_FLAG_DELAY_SLOT_MASK) {
151 /* Branch instruction should be executed again before delay slot. */
152 env->spc -= 2;
153 /* Clear flags for exception/interrupt routine. */
154 env->flags &= ~TB_FLAG_DELAY_SLOT_MASK;
155 }
156
157 if (do_exp) {
158 env->expevt = cs->exception_index;
159 switch (cs->exception_index) {
160 case 0x000:
161 case 0x020:
162 case 0x140:
163 env->sr &= ~(1u << SR_FD);
164 env->sr |= 0xf << 4; /* IMASK */
165 env->pc = 0xa0000000;
166 break;
167 case 0x040:
168 case 0x060:
169 env->pc = env->vbr + 0x400;
170 break;
171 case 0x160:
172 env->spc += 2; /* special case for TRAPA */
173 /* fall through */
174 default:
175 env->pc = env->vbr + 0x100;
176 break;
177 }
178 return;
179 }
180
181 if (do_irq) {
182 env->intevt = irq_vector;
183 env->pc = env->vbr + 0x600;
184 return;
185 }
186 }
187
update_itlb_use(CPUSH4State * env,int itlbnb)188 static void update_itlb_use(CPUSH4State * env, int itlbnb)
189 {
190 uint8_t or_mask = 0, and_mask = (uint8_t) - 1;
191
192 switch (itlbnb) {
193 case 0:
194 and_mask = 0x1f;
195 break;
196 case 1:
197 and_mask = 0xe7;
198 or_mask = 0x80;
199 break;
200 case 2:
201 and_mask = 0xfb;
202 or_mask = 0x50;
203 break;
204 case 3:
205 or_mask = 0x2c;
206 break;
207 }
208
209 env->mmucr &= (and_mask << 24) | 0x00ffffff;
210 env->mmucr |= (or_mask << 24);
211 }
212
itlb_replacement(CPUSH4State * env)213 static int itlb_replacement(CPUSH4State * env)
214 {
215 if ((env->mmucr & 0xe0000000) == 0xe0000000) {
216 return 0;
217 }
218 if ((env->mmucr & 0x98000000) == 0x18000000) {
219 return 1;
220 }
221 if ((env->mmucr & 0x54000000) == 0x04000000) {
222 return 2;
223 }
224 if ((env->mmucr & 0x2c000000) == 0x00000000) {
225 return 3;
226 }
227 cpu_abort(env_cpu(env), "Unhandled itlb_replacement");
228 }
229
230 /* Find the corresponding entry in the right TLB
231 Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
232 */
find_tlb_entry(CPUSH4State * env,target_ulong address,tlb_t * entries,uint8_t nbtlb,int use_asid)233 static int find_tlb_entry(CPUSH4State * env, target_ulong address,
234 tlb_t * entries, uint8_t nbtlb, int use_asid)
235 {
236 int match = MMU_DTLB_MISS;
237 uint32_t start, end;
238 uint8_t asid;
239 int i;
240
241 asid = env->pteh & 0xff;
242
243 for (i = 0; i < nbtlb; i++) {
244 if (!entries[i].v)
245 continue; /* Invalid entry */
246 if (!entries[i].sh && use_asid && entries[i].asid != asid)
247 continue; /* Bad ASID */
248 start = (entries[i].vpn << 10) & ~(entries[i].size - 1);
249 end = start + entries[i].size - 1;
250 if (address >= start && address <= end) { /* Match */
251 if (match != MMU_DTLB_MISS)
252 return MMU_DTLB_MULTIPLE; /* Multiple match */
253 match = i;
254 }
255 }
256 return match;
257 }
258
increment_urc(CPUSH4State * env)259 static void increment_urc(CPUSH4State * env)
260 {
261 uint8_t urb, urc;
262
263 /* Increment URC */
264 urb = ((env->mmucr) >> 18) & 0x3f;
265 urc = ((env->mmucr) >> 10) & 0x3f;
266 urc++;
267 if ((urb > 0 && urc > urb) || urc > (UTLB_SIZE - 1))
268 urc = 0;
269 env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10);
270 }
271
272 /* Copy and utlb entry into itlb
273 Return entry
274 */
copy_utlb_entry_itlb(CPUSH4State * env,int utlb)275 static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb)
276 {
277 int itlb;
278
279 tlb_t * ientry;
280 itlb = itlb_replacement(env);
281 ientry = &env->itlb[itlb];
282 if (ientry->v) {
283 tlb_flush_page(env_cpu(env), ientry->vpn << 10);
284 }
285 *ientry = env->utlb[utlb];
286 update_itlb_use(env, itlb);
287 return itlb;
288 }
289
290 /* Find itlb entry
291 Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
292 */
find_itlb_entry(CPUSH4State * env,target_ulong address,int use_asid)293 static int find_itlb_entry(CPUSH4State * env, target_ulong address,
294 int use_asid)
295 {
296 int e;
297
298 e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid);
299 if (e == MMU_DTLB_MULTIPLE) {
300 e = MMU_ITLB_MULTIPLE;
301 } else if (e == MMU_DTLB_MISS) {
302 e = MMU_ITLB_MISS;
303 } else if (e >= 0) {
304 update_itlb_use(env, e);
305 }
306 return e;
307 }
308
309 /* Find utlb entry
310 Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
find_utlb_entry(CPUSH4State * env,target_ulong address,int use_asid)311 static int find_utlb_entry(CPUSH4State * env, target_ulong address, int use_asid)
312 {
313 /* per utlb access */
314 increment_urc(env);
315
316 /* Return entry */
317 return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
318 }
319
320 /* Match address against MMU
321 Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
322 MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
323 MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
324 MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
325 MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
326 */
get_mmu_address(CPUSH4State * env,target_ulong * physical,int * prot,target_ulong address,MMUAccessType access_type)327 static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
328 int *prot, target_ulong address,
329 MMUAccessType access_type)
330 {
331 int use_asid, n;
332 tlb_t *matching = NULL;
333
334 use_asid = !(env->mmucr & MMUCR_SV) || !(env->sr & (1u << SR_MD));
335
336 if (access_type == MMU_INST_FETCH) {
337 n = find_itlb_entry(env, address, use_asid);
338 if (n >= 0) {
339 matching = &env->itlb[n];
340 if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) {
341 n = MMU_ITLB_VIOLATION;
342 } else {
343 *prot = PAGE_EXEC;
344 }
345 } else {
346 n = find_utlb_entry(env, address, use_asid);
347 if (n >= 0) {
348 n = copy_utlb_entry_itlb(env, n);
349 matching = &env->itlb[n];
350 if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) {
351 n = MMU_ITLB_VIOLATION;
352 } else {
353 *prot = PAGE_READ | PAGE_EXEC;
354 if ((matching->pr & 1) && matching->d) {
355 *prot |= PAGE_WRITE;
356 }
357 }
358 } else if (n == MMU_DTLB_MULTIPLE) {
359 n = MMU_ITLB_MULTIPLE;
360 } else if (n == MMU_DTLB_MISS) {
361 n = MMU_ITLB_MISS;
362 }
363 }
364 } else {
365 n = find_utlb_entry(env, address, use_asid);
366 if (n >= 0) {
367 matching = &env->utlb[n];
368 if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) {
369 n = (access_type == MMU_DATA_STORE)
370 ? MMU_DTLB_VIOLATION_WRITE : MMU_DTLB_VIOLATION_READ;
371 } else if ((access_type == MMU_DATA_STORE) && !(matching->pr & 1)) {
372 n = MMU_DTLB_VIOLATION_WRITE;
373 } else if ((access_type == MMU_DATA_STORE) && !matching->d) {
374 n = MMU_DTLB_INITIAL_WRITE;
375 } else {
376 *prot = PAGE_READ;
377 if ((matching->pr & 1) && matching->d) {
378 *prot |= PAGE_WRITE;
379 }
380 }
381 } else if (n == MMU_DTLB_MISS) {
382 n = (access_type == MMU_DATA_STORE)
383 ? MMU_DTLB_MISS_WRITE : MMU_DTLB_MISS_READ;
384 }
385 }
386 if (n >= 0) {
387 n = MMU_OK;
388 *physical = ((matching->ppn << 10) & ~(matching->size - 1))
389 | (address & (matching->size - 1));
390 }
391 return n;
392 }
393
get_physical_address(CPUSH4State * env,target_ulong * physical,int * prot,target_ulong address,MMUAccessType access_type)394 static int get_physical_address(CPUSH4State * env, target_ulong * physical,
395 int *prot, target_ulong address,
396 MMUAccessType access_type)
397 {
398 /* P1, P2 and P4 areas do not use translation */
399 if ((address >= 0x80000000 && address < 0xc0000000) || address >= 0xe0000000) {
400 if (!(env->sr & (1u << SR_MD))
401 && (address < 0xe0000000 || address >= 0xe4000000)) {
402 /* Unauthorized access in user mode (only store queues are available) */
403 qemu_log_mask(LOG_GUEST_ERROR, "Unauthorized access\n");
404 if (access_type == MMU_DATA_LOAD) {
405 return MMU_DADDR_ERROR_READ;
406 } else if (access_type == MMU_DATA_STORE) {
407 return MMU_DADDR_ERROR_WRITE;
408 } else {
409 return MMU_IADDR_ERROR;
410 }
411 }
412 if (address >= 0x80000000 && address < 0xc0000000) {
413 /* Mask upper 3 bits for P1 and P2 areas */
414 *physical = address & 0x1fffffff;
415 } else {
416 *physical = address;
417 }
418 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
419 return MMU_OK;
420 }
421
422 /* If MMU is disabled, return the corresponding physical page */
423 if (!(env->mmucr & MMUCR_AT)) {
424 *physical = address & 0x1FFFFFFF;
425 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
426 return MMU_OK;
427 }
428
429 /* We need to resort to the MMU */
430 return get_mmu_address(env, physical, prot, address, access_type);
431 }
432
superh_cpu_get_phys_page_debug(CPUState * cs,vaddr addr)433 hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
434 {
435 target_ulong physical;
436 int prot;
437
438 if (get_physical_address(cpu_env(cs), &physical, &prot, addr, MMU_DATA_LOAD)
439 == MMU_OK) {
440 return physical;
441 }
442
443 return -1;
444 }
445
cpu_load_tlb(CPUSH4State * env)446 void cpu_load_tlb(CPUSH4State * env)
447 {
448 CPUState *cs = env_cpu(env);
449 int n = cpu_mmucr_urc(env->mmucr);
450 tlb_t * entry = &env->utlb[n];
451
452 if (entry->v) {
453 /* Overwriting valid entry in utlb. */
454 target_ulong address = entry->vpn << 10;
455 tlb_flush_page(cs, address);
456 }
457
458 /* Take values into cpu status from registers. */
459 entry->asid = (uint8_t)cpu_pteh_asid(env->pteh);
460 entry->vpn = cpu_pteh_vpn(env->pteh);
461 entry->v = (uint8_t)cpu_ptel_v(env->ptel);
462 entry->ppn = cpu_ptel_ppn(env->ptel);
463 entry->sz = (uint8_t)cpu_ptel_sz(env->ptel);
464 switch (entry->sz) {
465 case 0: /* 00 */
466 entry->size = 1024; /* 1K */
467 break;
468 case 1: /* 01 */
469 entry->size = 1024 * 4; /* 4K */
470 break;
471 case 2: /* 10 */
472 entry->size = 1024 * 64; /* 64K */
473 break;
474 case 3: /* 11 */
475 entry->size = 1024 * 1024; /* 1M */
476 break;
477 default:
478 cpu_abort(cs, "Unhandled load_tlb");
479 break;
480 }
481 entry->sh = (uint8_t)cpu_ptel_sh(env->ptel);
482 entry->c = (uint8_t)cpu_ptel_c(env->ptel);
483 entry->pr = (uint8_t)cpu_ptel_pr(env->ptel);
484 entry->d = (uint8_t)cpu_ptel_d(env->ptel);
485 entry->wt = (uint8_t)cpu_ptel_wt(env->ptel);
486 entry->sa = (uint8_t)cpu_ptea_sa(env->ptea);
487 entry->tc = (uint8_t)cpu_ptea_tc(env->ptea);
488 }
489
cpu_sh4_invalidate_tlb(CPUSH4State * s)490 void cpu_sh4_invalidate_tlb(CPUSH4State *s)
491 {
492 int i;
493
494 /* UTLB */
495 for (i = 0; i < UTLB_SIZE; i++) {
496 tlb_t * entry = &s->utlb[i];
497 entry->v = 0;
498 }
499 /* ITLB */
500 for (i = 0; i < ITLB_SIZE; i++) {
501 tlb_t * entry = &s->itlb[i];
502 entry->v = 0;
503 }
504
505 tlb_flush(env_cpu(s));
506 }
507
cpu_sh4_read_mmaped_itlb_addr(CPUSH4State * s,hwaddr addr)508 uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
509 hwaddr addr)
510 {
511 int index = (addr & 0x00000300) >> 8;
512 tlb_t * entry = &s->itlb[index];
513
514 return (entry->vpn << 10) |
515 (entry->v << 8) |
516 (entry->asid);
517 }
518
cpu_sh4_write_mmaped_itlb_addr(CPUSH4State * s,hwaddr addr,uint32_t mem_value)519 void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
520 uint32_t mem_value)
521 {
522 uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
523 uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
524 uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
525
526 int index = (addr & 0x00000300) >> 8;
527 tlb_t * entry = &s->itlb[index];
528 if (entry->v) {
529 /* Overwriting valid entry in itlb. */
530 target_ulong address = entry->vpn << 10;
531 tlb_flush_page(env_cpu(s), address);
532 }
533 entry->asid = asid;
534 entry->vpn = vpn;
535 entry->v = v;
536 }
537
cpu_sh4_read_mmaped_itlb_data(CPUSH4State * s,hwaddr addr)538 uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
539 hwaddr addr)
540 {
541 int array = (addr & 0x00800000) >> 23;
542 int index = (addr & 0x00000300) >> 8;
543 tlb_t * entry = &s->itlb[index];
544
545 if (array == 0) {
546 /* ITLB Data Array 1 */
547 return (entry->ppn << 10) |
548 (entry->v << 8) |
549 (entry->pr << 5) |
550 ((entry->sz & 1) << 6) |
551 ((entry->sz & 2) << 4) |
552 (entry->c << 3) |
553 (entry->sh << 1);
554 } else {
555 /* ITLB Data Array 2 */
556 return (entry->tc << 1) |
557 (entry->sa);
558 }
559 }
560
cpu_sh4_write_mmaped_itlb_data(CPUSH4State * s,hwaddr addr,uint32_t mem_value)561 void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
562 uint32_t mem_value)
563 {
564 int array = (addr & 0x00800000) >> 23;
565 int index = (addr & 0x00000300) >> 8;
566 tlb_t * entry = &s->itlb[index];
567
568 if (array == 0) {
569 /* ITLB Data Array 1 */
570 if (entry->v) {
571 /* Overwriting valid entry in utlb. */
572 target_ulong address = entry->vpn << 10;
573 tlb_flush_page(env_cpu(s), address);
574 }
575 entry->ppn = (mem_value & 0x1ffffc00) >> 10;
576 entry->v = (mem_value & 0x00000100) >> 8;
577 entry->sz = (mem_value & 0x00000080) >> 6 |
578 (mem_value & 0x00000010) >> 4;
579 entry->pr = (mem_value & 0x00000040) >> 5;
580 entry->c = (mem_value & 0x00000008) >> 3;
581 entry->sh = (mem_value & 0x00000002) >> 1;
582 } else {
583 /* ITLB Data Array 2 */
584 entry->tc = (mem_value & 0x00000008) >> 3;
585 entry->sa = (mem_value & 0x00000007);
586 }
587 }
588
cpu_sh4_read_mmaped_utlb_addr(CPUSH4State * s,hwaddr addr)589 uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
590 hwaddr addr)
591 {
592 int index = (addr & 0x00003f00) >> 8;
593 tlb_t * entry = &s->utlb[index];
594
595 increment_urc(s); /* per utlb access */
596
597 return (entry->vpn << 10) |
598 (entry->v << 8) |
599 (entry->asid);
600 }
601
cpu_sh4_write_mmaped_utlb_addr(CPUSH4State * s,hwaddr addr,uint32_t mem_value)602 void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
603 uint32_t mem_value)
604 {
605 int associate = addr & 0x0000080;
606 uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
607 uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9);
608 uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
609 uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
610 int use_asid = !(s->mmucr & MMUCR_SV) || !(s->sr & (1u << SR_MD));
611
612 if (associate) {
613 int i;
614 tlb_t * utlb_match_entry = NULL;
615 int needs_tlb_flush = 0;
616
617 /* search UTLB */
618 for (i = 0; i < UTLB_SIZE; i++) {
619 tlb_t * entry = &s->utlb[i];
620 if (!entry->v)
621 continue;
622
623 if (entry->vpn == vpn
624 && (!use_asid || entry->asid == asid || entry->sh)) {
625 if (utlb_match_entry) {
626 CPUState *cs = env_cpu(s);
627
628 /* Multiple TLB Exception */
629 cs->exception_index = 0x140;
630 s->tea = addr;
631 break;
632 }
633 if (entry->v && !v)
634 needs_tlb_flush = 1;
635 entry->v = v;
636 entry->d = d;
637 utlb_match_entry = entry;
638 }
639 increment_urc(s); /* per utlb access */
640 }
641
642 /* search ITLB */
643 for (i = 0; i < ITLB_SIZE; i++) {
644 tlb_t * entry = &s->itlb[i];
645 if (entry->vpn == vpn
646 && (!use_asid || entry->asid == asid || entry->sh)) {
647 if (entry->v && !v)
648 needs_tlb_flush = 1;
649 if (utlb_match_entry)
650 *entry = *utlb_match_entry;
651 else
652 entry->v = v;
653 break;
654 }
655 }
656
657 if (needs_tlb_flush) {
658 tlb_flush_page(env_cpu(s), vpn << 10);
659 }
660 } else {
661 int index = (addr & 0x00003f00) >> 8;
662 tlb_t * entry = &s->utlb[index];
663 if (entry->v) {
664 CPUState *cs = env_cpu(s);
665
666 /* Overwriting valid entry in utlb. */
667 target_ulong address = entry->vpn << 10;
668 tlb_flush_page(cs, address);
669 }
670 entry->asid = asid;
671 entry->vpn = vpn;
672 entry->d = d;
673 entry->v = v;
674 increment_urc(s);
675 }
676 }
677
cpu_sh4_read_mmaped_utlb_data(CPUSH4State * s,hwaddr addr)678 uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
679 hwaddr addr)
680 {
681 int array = (addr & 0x00800000) >> 23;
682 int index = (addr & 0x00003f00) >> 8;
683 tlb_t * entry = &s->utlb[index];
684
685 increment_urc(s); /* per utlb access */
686
687 if (array == 0) {
688 /* ITLB Data Array 1 */
689 return (entry->ppn << 10) |
690 (entry->v << 8) |
691 (entry->pr << 5) |
692 ((entry->sz & 1) << 6) |
693 ((entry->sz & 2) << 4) |
694 (entry->c << 3) |
695 (entry->d << 2) |
696 (entry->sh << 1) |
697 (entry->wt);
698 } else {
699 /* ITLB Data Array 2 */
700 return (entry->tc << 1) |
701 (entry->sa);
702 }
703 }
704
cpu_sh4_write_mmaped_utlb_data(CPUSH4State * s,hwaddr addr,uint32_t mem_value)705 void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
706 uint32_t mem_value)
707 {
708 int array = (addr & 0x00800000) >> 23;
709 int index = (addr & 0x00003f00) >> 8;
710 tlb_t * entry = &s->utlb[index];
711
712 increment_urc(s); /* per utlb access */
713
714 if (array == 0) {
715 /* UTLB Data Array 1 */
716 if (entry->v) {
717 /* Overwriting valid entry in utlb. */
718 target_ulong address = entry->vpn << 10;
719 tlb_flush_page(env_cpu(s), address);
720 }
721 entry->ppn = (mem_value & 0x1ffffc00) >> 10;
722 entry->v = (mem_value & 0x00000100) >> 8;
723 entry->sz = (mem_value & 0x00000080) >> 6 |
724 (mem_value & 0x00000010) >> 4;
725 entry->pr = (mem_value & 0x00000060) >> 5;
726 entry->c = (mem_value & 0x00000008) >> 3;
727 entry->d = (mem_value & 0x00000004) >> 2;
728 entry->sh = (mem_value & 0x00000002) >> 1;
729 entry->wt = (mem_value & 0x00000001);
730 } else {
731 /* UTLB Data Array 2 */
732 entry->tc = (mem_value & 0x00000008) >> 3;
733 entry->sa = (mem_value & 0x00000007);
734 }
735 }
736
cpu_sh4_is_cached(CPUSH4State * env,target_ulong addr)737 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
738 {
739 int n;
740 int use_asid = !(env->mmucr & MMUCR_SV) || !(env->sr & (1u << SR_MD));
741
742 /* check area */
743 if (env->sr & (1u << SR_MD)) {
744 /* For privileged mode, P2 and P4 area is not cacheable. */
745 if ((0xA0000000 <= addr && addr < 0xC0000000) || 0xE0000000 <= addr)
746 return 0;
747 } else {
748 /* For user mode, only U0 area is cacheable. */
749 if (0x80000000 <= addr)
750 return 0;
751 }
752
753 /*
754 * TODO : Evaluate CCR and check if the cache is on or off.
755 * Now CCR is not in CPUSH4State, but in SH7750State.
756 * When you move the ccr into CPUSH4State, the code will be
757 * as follows.
758 */
759 #if 0
760 /* check if operand cache is enabled or not. */
761 if (!(env->ccr & 1))
762 return 0;
763 #endif
764
765 /* if MMU is off, no check for TLB. */
766 if (env->mmucr & MMUCR_AT)
767 return 1;
768
769 /* check TLB */
770 n = find_tlb_entry(env, addr, env->itlb, ITLB_SIZE, use_asid);
771 if (n >= 0)
772 return env->itlb[n].c;
773
774 n = find_tlb_entry(env, addr, env->utlb, UTLB_SIZE, use_asid);
775 if (n >= 0)
776 return env->utlb[n].c;
777
778 return 0;
779 }
780
superh_cpu_exec_interrupt(CPUState * cs,int interrupt_request)781 bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
782 {
783 if (interrupt_request & CPU_INTERRUPT_HARD) {
784 /* Delay slots are indivisible, ignore interrupts */
785 if (cpu_env(cs)->flags & TB_FLAG_DELAY_SLOT_MASK) {
786 return false;
787 } else {
788 superh_cpu_do_interrupt(cs);
789 return true;
790 }
791 }
792 return false;
793 }
794
superh_cpu_tlb_fill(CPUState * cs,vaddr address,int size,MMUAccessType access_type,int mmu_idx,bool probe,uintptr_t retaddr)795 bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
796 MMUAccessType access_type, int mmu_idx,
797 bool probe, uintptr_t retaddr)
798 {
799 CPUSH4State *env = cpu_env(cs);
800 int ret;
801
802 target_ulong physical;
803 int prot;
804
805 ret = get_physical_address(env, &physical, &prot, address, access_type);
806
807 if (ret == MMU_OK) {
808 address &= TARGET_PAGE_MASK;
809 physical &= TARGET_PAGE_MASK;
810 tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
811 return true;
812 }
813 if (probe) {
814 return false;
815 }
816
817 if (ret != MMU_DTLB_MULTIPLE && ret != MMU_ITLB_MULTIPLE) {
818 env->pteh = (env->pteh & PTEH_ASID_MASK) | (address & PTEH_VPN_MASK);
819 }
820
821 env->tea = address;
822 switch (ret) {
823 case MMU_ITLB_MISS:
824 case MMU_DTLB_MISS_READ:
825 cs->exception_index = 0x040;
826 break;
827 case MMU_DTLB_MULTIPLE:
828 case MMU_ITLB_MULTIPLE:
829 cs->exception_index = 0x140;
830 break;
831 case MMU_ITLB_VIOLATION:
832 cs->exception_index = 0x0a0;
833 break;
834 case MMU_DTLB_MISS_WRITE:
835 cs->exception_index = 0x060;
836 break;
837 case MMU_DTLB_INITIAL_WRITE:
838 cs->exception_index = 0x080;
839 break;
840 case MMU_DTLB_VIOLATION_READ:
841 cs->exception_index = 0x0a0;
842 break;
843 case MMU_DTLB_VIOLATION_WRITE:
844 cs->exception_index = 0x0c0;
845 break;
846 case MMU_IADDR_ERROR:
847 case MMU_DADDR_ERROR_READ:
848 cs->exception_index = 0x0e0;
849 break;
850 case MMU_DADDR_ERROR_WRITE:
851 cs->exception_index = 0x100;
852 break;
853 default:
854 cpu_abort(cs, "Unhandled MMU fault");
855 }
856 cpu_loop_exit_restore(cs, retaddr);
857 }
858 #endif /* !CONFIG_USER_ONLY */
859