Searched refs:RVH (Results 1 – 10 of 10) sorted by relevance
/qemu/target/riscv/insn_trans/ |
H A D | trans_rvh.c.inc | 67 REQUIRE_EXT(ctx, RVH); 73 REQUIRE_EXT(ctx, RVH); 79 REQUIRE_EXT(ctx, RVH); 85 REQUIRE_EXT(ctx, RVH); 91 REQUIRE_EXT(ctx, RVH); 97 REQUIRE_EXT(ctx, RVH); 103 REQUIRE_EXT(ctx, RVH); 109 REQUIRE_EXT(ctx, RVH); 116 REQUIRE_EXT(ctx, RVH); 123 REQUIRE_EXT(ctx, RVH); [all …]
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H A D | trans_svinval.c.inc | 58 REQUIRE_EXT(ctx, RVH); 71 REQUIRE_EXT(ctx, RVH);
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/qemu/target/riscv/tcg/ |
H A D | tcg-cpu.c | 258 if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { in riscv_cpu_validate_misa_priv() 438 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { in riscv_cpu_validate_set_extensions() 444 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { in riscv_cpu_validate_set_extensions() 933 if (riscv_has_ext(env, RVH)) { in riscv_tcg_cpu_realize() 976 if (misa_bit == RVH && env->priv_ver < PRIV_VERSION_1_12_0) { in cpu_set_misa_ext_cfg() 1015 MISA_CFG(RVH, true),
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/qemu/target/riscv/ |
H A D | op_helper.c | 297 if (riscv_has_ext(env, RVH) && !env->virt_enabled) { in helper_sret() 352 if (riscv_has_ext(env, RVH)) { in helper_mret()
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H A D | cpu_helper.c | 549 g_assert(riscv_has_ext(env, RVH)); in riscv_cpu_swap_hypervisor_regs() 602 if (!riscv_has_ext(env, RVH)) { in riscv_cpu_get_geilen() 611 if (!riscv_has_ext(env, RVH)) { in riscv_cpu_set_geilen() 1757 if (riscv_has_ext(env, RVH)) { in riscv_cpu_do_interrupt() 1805 if (riscv_has_ext(env, RVH)) { in riscv_cpu_do_interrupt()
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H A D | cpu.c | 45 RVC, RVS, RVU, RVH, RVJ, RVG, RVB, 0}; 562 riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH); in rv64_veyron_v1_cpu_init() 764 if (riscv_has_ext(env, RVH)) { in riscv_cpu_dump_state() 953 if (riscv_has_ext(env, RVH)) { in riscv_cpu_reset_hold() 996 if (riscv_has_ext(env, RVH)) { in riscv_cpu_reset_hold() 1284 if (!riscv_has_ext(env, RVH)) { in riscv_cpu_set_irq() 1403 MISA_EXT_INFO(RVH, "h", "Hypervisor"),
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H A D | machine.c | 77 return riscv_has_ext(env, RVH); in hyper_needed()
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H A D | csr.c | 301 if (riscv_has_ext(env, RVH)) { in hmode() 1384 if (riscv_has_ext(env, RVH)) { in write_mstatus() 1419 uint64_t mask = riscv_has_ext(env, RVH) ? MSTATUS_MPV | MSTATUS_GVA : 0; in write_mstatush() 1546 if (riscv_has_ext(env, RVH)) { in rmw_mideleg64() 1597 if (!riscv_has_ext(env, RVH)) { in rmw_mie64() 3959 if (riscv_has_ext(env, RVH)) { in write_mcontext() 4366 if (riscv_has_ext(env, RVH) && env->priv == PRV_S && in riscv_csrrw_check()
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H A D | cpu.h | 68 #define RVH RV('H') macro
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/qemu/target/riscv/kvm/ |
H A D | kvm-cpu.c | 183 KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H),
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