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Searched refs:RVH (Results 1 – 10 of 10) sorted by relevance

/qemu/target/riscv/insn_trans/
H A Dtrans_rvh.c.inc67 REQUIRE_EXT(ctx, RVH);
73 REQUIRE_EXT(ctx, RVH);
79 REQUIRE_EXT(ctx, RVH);
85 REQUIRE_EXT(ctx, RVH);
91 REQUIRE_EXT(ctx, RVH);
97 REQUIRE_EXT(ctx, RVH);
103 REQUIRE_EXT(ctx, RVH);
109 REQUIRE_EXT(ctx, RVH);
116 REQUIRE_EXT(ctx, RVH);
123 REQUIRE_EXT(ctx, RVH);
[all …]
H A Dtrans_svinval.c.inc58 REQUIRE_EXT(ctx, RVH);
71 REQUIRE_EXT(ctx, RVH);
/qemu/target/riscv/tcg/
H A Dtcg-cpu.c258 if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { in riscv_cpu_validate_misa_priv()
438 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { in riscv_cpu_validate_set_extensions()
444 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { in riscv_cpu_validate_set_extensions()
933 if (riscv_has_ext(env, RVH)) { in riscv_tcg_cpu_realize()
976 if (misa_bit == RVH && env->priv_ver < PRIV_VERSION_1_12_0) { in cpu_set_misa_ext_cfg()
1015 MISA_CFG(RVH, true),
/qemu/target/riscv/
H A Dop_helper.c297 if (riscv_has_ext(env, RVH) && !env->virt_enabled) { in helper_sret()
352 if (riscv_has_ext(env, RVH)) { in helper_mret()
H A Dcpu_helper.c549 g_assert(riscv_has_ext(env, RVH)); in riscv_cpu_swap_hypervisor_regs()
602 if (!riscv_has_ext(env, RVH)) { in riscv_cpu_get_geilen()
611 if (!riscv_has_ext(env, RVH)) { in riscv_cpu_set_geilen()
1757 if (riscv_has_ext(env, RVH)) { in riscv_cpu_do_interrupt()
1805 if (riscv_has_ext(env, RVH)) { in riscv_cpu_do_interrupt()
H A Dcpu.c45 RVC, RVS, RVU, RVH, RVJ, RVG, RVB, 0};
562 riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH); in rv64_veyron_v1_cpu_init()
764 if (riscv_has_ext(env, RVH)) { in riscv_cpu_dump_state()
953 if (riscv_has_ext(env, RVH)) { in riscv_cpu_reset_hold()
996 if (riscv_has_ext(env, RVH)) { in riscv_cpu_reset_hold()
1284 if (!riscv_has_ext(env, RVH)) { in riscv_cpu_set_irq()
1403 MISA_EXT_INFO(RVH, "h", "Hypervisor"),
H A Dmachine.c77 return riscv_has_ext(env, RVH); in hyper_needed()
H A Dcsr.c301 if (riscv_has_ext(env, RVH)) { in hmode()
1384 if (riscv_has_ext(env, RVH)) { in write_mstatus()
1419 uint64_t mask = riscv_has_ext(env, RVH) ? MSTATUS_MPV | MSTATUS_GVA : 0; in write_mstatush()
1546 if (riscv_has_ext(env, RVH)) { in rmw_mideleg64()
1597 if (!riscv_has_ext(env, RVH)) { in rmw_mie64()
3959 if (riscv_has_ext(env, RVH)) { in write_mcontext()
4366 if (riscv_has_ext(env, RVH) && env->priv == PRV_S && in riscv_csrrw_check()
H A Dcpu.h68 #define RVH RV('H') macro
/qemu/target/riscv/kvm/
H A Dkvm-cpu.c183 KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H),