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/qemu/target/hexagon/idef-parser/
H A Dmacros.inc40 #define fCLIP(DST, SRC, U) (DST = fMIN((1 << U) - 1, fMAX(SRC, -(1 << U))))
44 (fCAST##REGSTYPE##s(SRC) >> -SHAMT))
49 (fCAST##REGSTYPE##u(SRC) >>> -SHAMT))
54 (fCAST##REGSTYPE##s(SRC) << -SHAMT))
56 #define fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE) \
61 fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE##u)
82 : fSAT_ORIG_SHL(fCAST##REGSTYPE##s(SRC) << (SHAMT), (SRC)))
122 #define fASHIFTR(SRC, SHAMT, REGSTYPE) (fCAST##REGSTYPE##s(SRC) >> SHAMT)
123 #define fLSHIFTR(SRC, SHAMT, REGSTYPE) (SRC >>> SHAMT)
124 #define fROTL(SRC, SHAMT, REGSTYPE) fROTL(SRC, SHAMT)
[all …]
/qemu/target/hexagon/
H A Dmacros.h510 (((SHAMT) == 0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) << (SHAMT)) | \
556 #define fSTORE(NUM, SIZE, EA, SRC) MEM_STORE##SIZE(EA, SRC, slot)
570 #define fGETBYTE(N, SRC) GETBYTE_FUNC(SRC)(BYTE, N, SRC, true)
571 #define fGETUBYTE(N, SRC) GETBYTE_FUNC(SRC)(BYTE, N, SRC, false)
573 #define fGETBYTE(N, SRC) ((int8_t)((SRC >> ((N) * 8)) & 0xff))
574 #define fGETUBYTE(N, SRC) ((uint8_t)((SRC >> ((N) * 8)) & 0xff))
584 #define fGETHALF(N, SRC) gen_get_half(HALF, N, SRC, true)
585 #define fGETUHALF(N, SRC) gen_get_half(HALF, N, SRC, false)
587 #define fGETHALF(N, SRC) ((int16_t)((SRC >> ((N) * 16)) & 0xffff))
588 #define fGETUHALF(N, SRC) ((uint16_t)((SRC >> ((N) * 16)) & 0xffff))
[all …]
/qemu/scripts/
H A Dentitlement.sh12 SRC="$2"
18 cp -pPf "$SRC" "$DST.tmp"
19 SRC="$DST.tmp"
25 codesign --entitlements "$ENTITLEMENT" --force -s - "$SRC"
29 Rez -append "$ICON" -o "$SRC"
30 SetFile -a C "$SRC"
32 mv -f "$SRC" "$DST"
/qemu/target/hexagon/imported/
H A Dmacros.def806 DST = fMIN(maxv,fMAX(SRC,minv));
988 …(((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) >> ((-(SHAMT))-1)) >>1) : (fCAST##REGSTYPE(SRC) << (SHAMT)…
1006 …HAMT) < 0) ? ((fCAST##REGSTYPE##s(SRC) >> ((-(SHAMT))-1)) >>1) : fSAT_ORIG_SHL(fCAST##REGSTYPE##s(…
1013 …(((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) << ((-(SHAMT))-1)) << 1) : (fCAST##REGSTYPE(SRC) >> (SHAMT…
1031 …AMT) < 0) ? fSAT_ORIG_SHL((fCAST##REGSTYPE##s(SRC) << ((-(SHAMT))-1)) << 1,(SRC)) : (fCAST##REGSTY…
1049 (((SHAMT)==0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) << (SHAMT)) | \
1050 ((fCAST##REGSTYPE##u(SRC) >> ((sizeof(SRC)*8)-(SHAMT)))))),
1056 (((SHAMT)==0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) >> (SHAMT)) | \
1057 ((fCAST##REGSTYPE##u(SRC) << ((sizeof(SRC)*8)-(SHAMT)))))),
1387 ((size1s_t)((SRC>>((N)*8))&0xff)),
[all …]
H A Dfloat.idef314 #define CONVERT(TAG,DEST,DESTV,SRC,SRCV,OUTCAST,OUTTYPE,INCAST,INTYPE,MODETAG,MODESYN,MODEBEH) \
315 Q6INSN(F2_conv_##TAG##MODETAG,#DEST"=convert_"#TAG"("#SRC")"#MODESYN,ATTRIBS(), \
322 #define ALLINTDST(TAGSTART,SRC,SRCV,INCAST,INTYPE,MODETAG,MODESYN,MODEBEH) \
323 CONVERT(TAGSTART##uw,Rd32,RdV,SRC,SRCV,fCAST4u,4u,INCAST,INTYPE,MODETAG,MODESYN,MODEBEH) \
324 CONVERT(TAGSTART##w,Rd32,RdV,SRC,SRCV,fCAST4s,4s,INCAST,INTYPE,MODETAG,MODESYN,MODEBEH) \
325 CONVERT(TAGSTART##ud,Rdd32,RddV,SRC,SRCV,fCAST8u,8u,INCAST,INTYPE,MODETAG,MODESYN,MODEBEH) \
326 CONVERT(TAGSTART##d,Rdd32,RddV,SRC,SRCV,fCAST8s,8s,INCAST,INTYPE,MODETAG,MODESYN,MODEBEH)
328 #define ALLFPDST(TAGSTART,SRC,SRCV,INCAST,INTYPE,MODETAG,MODESYN,MODEBEH) \
329 CONVERT(TAGSTART##sf,Rd32,RdV,SRC,SRCV,fUNFLOAT,sf,INCAST,INTYPE,MODETAG,MODESYN,MODEBEH) \
330 CONVERT(TAGSTART##df,Rdd32,RddV,SRC,SRCV,fUNDOUBLE,df,INCAST,INTYPE,MODETAG,MODESYN,MODEBEH)
H A Dencode_pp.def99 #define STD_PST_IOENC(TAG,OPC,SRC) \
135 #define STD_ST_GP(TAG,OPC,SRC) \
136 DEF_ENC32(S2_store##TAG##gp, ICLASS_V2LDST" 1ii0 "OPC" iiiii PPi"SRC" iiiiiiii")
187 #define STD_PST_RRENC(TAG,OPC,SRC) \
234 #define STD_ST_RRENC(TAG,OPC,SRC) \
441 #define STD_ST_ENC(TAG,OPC,SRC) \
442 DEF_ENC32(S2_store##TAG##_io, ICLASS_ST" 0 ii "OPC" sssss PPi"SRC" iiiiiiii")\
443 DEF_ENC32(S2_store##TAG##_pci, ICLASS_ST" 1 00 "OPC" xxxxx PPu"SRC" 0iiii-0-")\
444 DEF_ENC32(S2_store##TAG##_pi, ICLASS_ST" 1 01 "OPC" xxxxx PP0"SRC" 0iiii-0-")\
449 DEF_ENC32(S2_store##TAG##_pbr, ICLASS_ST" 1 11 "OPC" xxxxx PPu"SRC" 0-------")
[all …]
H A Dalu.idef1129 #define CROUND(DST,SRC,SHIFT) \
1134 DST = SRC;\
1135 } else if ((SRC & (size8s_t)((1LL << (SHIFT - 1)) - 1LL)) == 0) { \
1136 src_128 = fCAST8S_16S(SRC);\
1146 src_128 = fCAST8S_16S(SRC); \
/qemu/target/hexagon/mmvec/
H A Dmacros.h76 #define fGETNIBBLE(IDX, SRC) (fSXTN(4, 8, (SRC >> (4 * IDX)) & 0xF))
77 #define fGETCRUMB(IDX, SRC) (fSXTN(2, 8, (SRC >> (2 * IDX)) & 0x3))
78 #define fGETCRUMB_SYMMETRIC(IDX, SRC) \
79 ((fGETCRUMB(IDX, SRC) >= 0 ? (2 - fGETCRUMB(IDX, SRC)) \
80 : fGETCRUMB(IDX, SRC)))
289 #define fSTOREMMV(EA, SRC) \
290 gen_vreg_store(ctx, EA, SRC##_off, insn->slot, true)
293 #define fSTOREMMVQ(EA, SRC, MASK) \
297 #define fSTOREMMVNQ(EA, SRC, MASK) \
301 #define fSTOREMMVU(EA, SRC) \
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/qemu/target/hexagon/imported/mmvec/
H A Dmacros.def72 ( fSXTN(4,8,(SRC >> (4*IDX)) & 0xF) ),
77 ( fSXTN(2,8,(SRC >> (2*IDX)) & 0x3) ),
82 ( (fGETCRUMB(IDX,SRC)>=0 ? (2-fGETCRUMB(IDX,SRC)) : fGETCRUMB(IDX,SRC) ) ),
591 fSTOREMMV_AL(EA,fVECSIZE(),fVECSIZE(),SRC),
606 fSTOREMMVQ_AL(EA,fVECSIZE(),fVECSIZE(),SRC,MASK),
622 fSTOREMMVNQ_AL(EA,fVECSIZE(),fVECSIZE(),SRC,MASK),
644 fSTOREMMV_AL(EA,fVECSIZE(),fVECSIZE(),SRC);
648 fSTOREMMVU_AL(EA,fVECSIZE(),fVECSIZE(),SRC);
675 fSTOREMMVQ_AL(EA,fVECSIZE(),fVECSIZE(),SRC,MASK);
679 fSTOREMMVQU_AL(EA,fVECSIZE(),fVECSIZE(),SRC,MASK);
[all …]
H A Dext.idef1108 …SRC",Vv32."#SRC")" , "Vector Absolute of Difference "DESCR, VdV.DEST[i] = (VuV.SRC[i] > VvV.…
1112 …SRC",Vvv32."#SRC"):sat", "Double Vector Add & Saturate "DESCR, VddV.v[0].DEST[i] = fVUADDSAT(WI…
1114 …SRC",Vvv32."#SRC"):sat", "Double Vector Add & Saturate "DESCR, VddV.v[0].DEST[i] = fVUSUBSAT(WI…
1118 …SRC",Vvv32."#SRC"):sat", "Double Vector Add & Saturate "DESCR, VddV.v[0].DEST[i] = fVSADDSAT(WI…
1120 …SRC",Vvv32."#SRC"):sat", "Double Vector Add & Saturate "DESCR, VddV.v[0].DEST[i] = fVSSUBSAT(WI…
1140 …, "Vd32."#DEST"=vadd(Vu32."#SRC",Vv32."#SRC")", "Vector Add "DESCR, VdV.DEST[i] = …
1141 …, "Vd32."#DEST"=vsub(Vu32."#SRC",Vv32."#SRC")", "Vector Sub "DESCR, VdV.DEST[i] = …
1142 …SRC",Vvv32."#SRC")", "Double Vector Add "DESCR, VddV.v[0].DEST[i] = VuuV.v[0].SRC[i] + VvvV.v[0]…
1143 …SRC",Vvv32."#SRC")", "Double Vector Sub "DESCR, VddV.v[0].DEST[i] = VuuV.v[0].SRC[i] - VvvV.v[0]…
1837 …v32)", "Vd32."#SRC"=vmax(Vu32."#SRC",Vv32."#SRC")", "Vector " DESCR " max", VdV.SRC[i] = (VuV.SRC[…
[all …]
/qemu/docs/system/arm/
H A Dversatile.rst37 In the following example $BLD points to the build directory and $SRC
38 points to the root of the Linux source tree. You can drop $SRC if you
43 $ make O=$BLD -C $SRC ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- versatile_defconfig
44 $ make O=$BLD -C $SRC ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-
H A Dvexpress.rst71 In the following example $BLD points to the build directory and $SRC
72 points to the root of the Linux source tree. You can drop $SRC if you
77 $ make O=$BLD -C $SRC ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- multi_v7_defconfig
78 $ make O=$BLD -C $SRC ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-
/qemu/tests/tcg/hexagon/
H A Dusr.c426 SRCTYPE src = SRC; \
433 #define TEST_R_OP_R(FUNC, SRC, RES, USR_RES) \ argument
434 TEST_x_OP_x(uint32_t, check32, uint32_t, FUNC, SRC, RES, USR_RES)
436 #define TEST_R_OP_P(FUNC, SRC, RES, USR_RES) \ argument
437 TEST_x_OP_x(uint32_t, check32, uint64_t, FUNC, SRC, RES, USR_RES)
439 #define TEST_P_OP_P(FUNC, SRC, RES, USR_RES) \ argument
440 TEST_x_OP_x(uint64_t, check64, uint64_t, FUNC, SRC, RES, USR_RES)
442 #define TEST_P_OP_R(FUNC, SRC, RES, USR_RES) \ argument
445 #define TEST_xp_OP_x(RESTYPE, CHECKFN, SRCTYPE, FUNC, SRC, \ argument
449 SRCTYPE src = SRC; \
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/qemu/
H A D.patchew.yml163 SRC=$PWD
165 $SRC/configure --cc=$CC --prefix=$INSTALL
192 SRC=$PWD
194 $SRC/configure --cc=$CC --prefix=$INSTALL
246 SRC=$PWD
248 $SRC/configure --cc=$CC --prefix=$INSTALL
/qemu/target/alpha/
H A Dhelper.c30 #define CONVERT_BIT(X, SRC, DST) \ argument
31 (SRC > DST ? (X) / (SRC / DST) & (DST) : ((X) & SRC) * (DST / SRC))
H A Dfpu_helper.c39 #define CONVERT_BIT(X, SRC, DST) \ argument
40 (SRC > DST ? (X) / (SRC / DST) & (DST) : ((X) & SRC) * (DST / SRC))
/qemu/target/hppa/
H A Dfpu_helper.c59 #define CONVERT_BIT(X, SRC, DST) \ argument
60 ((unsigned)(SRC) > (unsigned)(DST) \
61 ? (X) / ((SRC) / (DST)) & (DST) \
62 : ((X) & (SRC)) * ((DST) / (SRC)))
/qemu/target/sparc/
H A Dcpu.h359 #define CONVERT_BIT(X, SRC, DST) \ argument
360 (SRC > DST ? (X) / (SRC / DST) & (DST) : ((X) & SRC) * (DST / SRC))
/qemu/hw/misc/
H A Dbcm2835_cprman.c265 uint32_t div, src = FIELD_EX32(*mux->reg_ctl, CM_CLOCKx_CTL, SRC); in clock_mux_update()
314 if (FIELD_EX32(*s->reg_ctl, CM_CLOCKx_CTL, SRC) != src) { in clock_mux_src_update()
/qemu/include/hw/misc/
H A Dbcm2835_cprman_internals.h139 FIELD(CM_CLOCKx_CTL, SRC, 0, 4)
/qemu/target/i386/tcg/
H A Demit.c.inc1224 /* Compute adjusted DST in T1, merging in SRC[RPL]. */
1227 /* Z flag set if DST[RPL] < SRC[RPL] */