Searched refs:STORE (Results 1 – 10 of 10) sorted by relevance
/qemu/docs/devel/ |
H A D | atomics.rst | 125 components of the system, before all the LOAD or STORE operations 129 components of the system, after all the LOAD or STORE operations 145 before all the LOAD or STORE operations specified afterwards. 149 - ``qatomic_store_release()``, which guarantees the STORE to appear to 151 after all the LOAD or STORE operations specified before. 170 - ``smp_wmb()`` guarantees that all the STORE operations specified before 171 the barrier will appear to happen before all the STORE operations 179 the barrier will appear to happen before all the LOAD or STORE operations 184 the barrier will appear to happen after all the LOAD or STORE operations 188 - ``smp_mb()`` guarantees that all the LOAD and STORE operations specified [all …]
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/qemu/target/s390x/tcg/ |
H A D | insn-data.h.inc | 847 /* STORE */ 867 /* STORE HALFWORD */ 874 /* STORE HIGH */ 881 /* STORE REVERSED */ 886 /* STORE CLOCK */ 894 /* STORE FPC */ 897 /* STORE MULTIPLE */ 1095 /* VECTOR STORE */ 1394 /* STORE CONTROL */ 1399 /* STORE CPU ID */ [all …]
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/qemu/linux-user/arm/nwfpe/ |
H A D | fpopcode.h | 223 #define STORE(opcode) ((opcode & BIT_LOAD) == 0) macro
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/qemu/target/hexagon/idef-parser/ |
H A D | idef-parser.y | 55 %token ZXT CONSTEXT LOCNT BREV SIGN LOAD STORE PC LPCFG 348 | STORE '(' IMM ',' IMM ',' var ',' rvalue ')'
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/qemu/target/hexagon/ |
H A D | attribs_def.h.inc | 40 DEF_ATTRIB(STORE, "Stores to memory", "", "")
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H A D | gen_tcg.h | 422 #define fGEN_TCG_STORE_pcr(SHIFT, STORE) \ argument 430 STORE; \
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/qemu/target/riscv/ |
H A D | insn32.decode | 350 # *** Vector loads and stores are encoded within LOADFP/STORE-FP ***
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/qemu/target/hexagon/imported/ |
H A D | encode_pp.def | 415 /* STORE */
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/qemu/tcg/s390x/ |
H A D | tcg-target.c.inc | 3419 /* Is STORE FACILITY LIST EXTENDED available? Honestly, I believe this
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/qemu/target/mips/tcg/ |
H A D | translate.c | 1857 #define FOP_CONDNS(fmt, ifmt, bits, STORE) \ argument 1938 STORE; \
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