/qemu/target/i386/ |
H A D | xsave_helper.c | 46 stq_p(xmm, env->xmm_regs[i].ZMM_Q(0)); in x86_cpu_xsave_all_areas() 47 stq_p(xmm + 8, env->xmm_regs[i].ZMM_Q(1)); in x86_cpu_xsave_all_areas() 61 stq_p(ymmh, env->xmm_regs[i].ZMM_Q(2)); in x86_cpu_xsave_all_areas() 62 stq_p(ymmh + 8, env->xmm_regs[i].ZMM_Q(3)); in x86_cpu_xsave_all_areas() 104 stq_p(zmmh, env->xmm_regs[i].ZMM_Q(4)); in x86_cpu_xsave_all_areas() 105 stq_p(zmmh + 8, env->xmm_regs[i].ZMM_Q(5)); in x86_cpu_xsave_all_areas() 106 stq_p(zmmh + 16, env->xmm_regs[i].ZMM_Q(6)); in x86_cpu_xsave_all_areas() 180 env->xmm_regs[i].ZMM_Q(0) = ldq_p(xmm); in x86_cpu_xrstor_all_areas() 181 env->xmm_regs[i].ZMM_Q(1) = ldq_p(xmm + 8); in x86_cpu_xrstor_all_areas() 194 env->xmm_regs[i].ZMM_Q(2) = ldq_p(ymmh); in x86_cpu_xrstor_all_areas() [all …]
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H A D | cpu-dump.c | 518 env->xmm_regs[i].ZMM_Q(7), in x86_cpu_dump_state() 519 env->xmm_regs[i].ZMM_Q(6), in x86_cpu_dump_state() 520 env->xmm_regs[i].ZMM_Q(5), in x86_cpu_dump_state() 521 env->xmm_regs[i].ZMM_Q(4), in x86_cpu_dump_state() 522 env->xmm_regs[i].ZMM_Q(3), in x86_cpu_dump_state() 523 env->xmm_regs[i].ZMM_Q(2), in x86_cpu_dump_state() 524 env->xmm_regs[i].ZMM_Q(1), in x86_cpu_dump_state() 533 env->xmm_regs[i].ZMM_Q(3), in x86_cpu_dump_state() 534 env->xmm_regs[i].ZMM_Q(2), in x86_cpu_dump_state() 535 env->xmm_regs[i].ZMM_Q(1), in x86_cpu_dump_state() [all …]
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H A D | machine.c | 47 VMSTATE_UINT64(ZMM_Q(0), ZMMReg), 48 VMSTATE_UINT64(ZMM_Q(1), ZMMReg), 63 VMSTATE_UINT64(ZMM_Q(2), ZMMReg), 64 VMSTATE_UINT64(ZMM_Q(3), ZMMReg), 78 VMSTATE_UINT64(ZMM_Q(4), ZMMReg), 79 VMSTATE_UINT64(ZMM_Q(5), ZMMReg), 80 VMSTATE_UINT64(ZMM_Q(6), ZMMReg), 81 VMSTATE_UINT64(ZMM_Q(7), ZMMReg), 96 VMSTATE_UINT64(ZMM_Q(0), ZMMReg), 97 VMSTATE_UINT64(ZMM_Q( [all...] |
H A D | gdbstub.c | 134 env->xmm_regs[n].ZMM_Q(1), in x86_cpu_gdb_read_register() 135 env->xmm_regs[n].ZMM_Q(0)); in x86_cpu_gdb_read_register() 284 env->xmm_regs[n].ZMM_Q(0) = ldq_p(mem_buf); in x86_cpu_gdb_write_register() 285 env->xmm_regs[n].ZMM_Q(1) = ldq_p(mem_buf + 8); in x86_cpu_gdb_write_register()
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H A D | ops_sse.h | 39 #define Q(n) ZMM_Q(n) 504 d->ZMM_Q(i) = v->ZMM_Q(i); \ 566 d->ZMM_Q(i) = v->ZMM_Q(i); in helper_sqrtsd() 626 d->ZMM_Q(i) = v->ZMM_Q(i); in helper_cvtss2sd() 908 d->ZMM_Q(0) = helper_extrq(d->ZMM_Q(0), s->ZMM_B(1) & 63, s->ZMM_B(0) & 63); in helper_extrq_r() 913 d->ZMM_Q(0) = helper_extrq(d->ZMM_Q(0), index, length); in helper_extrq_i() 930 d->ZMM_Q(0) = helper_insertq(d->ZMM_Q(0), s->ZMM_Q(0), s->ZMM_B(9) & 63, s->ZMM_B(8) & 63); in helper_insertq_r() 935 d->ZMM_Q(0) = helper_insertq(d->ZMM_Q(0), s->ZMM_Q(0), index, length); in helper_insertq_i() 1035 d->ZMM_Q(i) = v->ZMM_Q(i); \ 1173 mask |= (s->ZMM_Q(i) >> (63 - i)) & (1 << i); in glue() [all …]
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H A D | cpu.h | 1397 #define ZMM_Q(n) _q_ZMMReg[7 - (n)] 1417 #define ZMM_Q(n) _q_ZMMReg[n] 1360 #define ZMM_Q( global() macro 1380 #define ZMM_Q( global() macro
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/qemu/target/i386/tcg/ |
H A D | fpu_helper.c | 2578 access_stq(ac, addr, env->xmm_regs[i].ZMM_Q(0)); in do_xsave_sse() 2579 access_stq(ac, addr + 8, env->xmm_regs[i].ZMM_Q(1)); in do_xsave_sse() 2596 access_stq(ac, ptr, env->xmm_regs[i].ZMM_Q(2)); in do_xsave_ymmh() 2597 access_stq(ac, ptr + 8, env->xmm_regs[i].ZMM_Q(3)); in do_xsave_ymmh() 2794 env->xmm_regs[i].ZMM_Q(0) = access_ldq(ac, addr); in do_xrstor_sse() 2811 env->xmm_regs[i].ZMM_Q(0) = 0; in do_clear_sse() 2812 env->xmm_regs[i].ZMM_Q(1) = 0; in do_clear_sse() 2828 env->xmm_regs[i].ZMM_Q(2) = access_ldq(ac, ptr); in do_xrstor_ymmh() 2829 env->xmm_regs[i].ZMM_Q(3) = access_ldq(ac, ptr + 8); in do_xrstor_ymmh() 2844 env->xmm_regs[i].ZMM_Q(2) = 0; in do_clear_ymmh() [all …]
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H A D | emit.c.inc | 108 return offsetof(ZMMReg, ZMM_Q(0)); 155 return base_ofs + offsetof(ZMMReg, ZMM_Q(n)); 2558 tcg_gen_ld_tl(t, tcg_env, offsetof(CPUX86State, xmm_t0.ZMM_Q((vec_len - 1) / 8))); 3893 tcg_gen_st_i64(s->tmp1_i64, OP_PTR0, offsetof(ZMMReg, ZMM_Q(0))); 3898 tcg_gen_ld_i64(s->tmp1_i64, OP_PTR2, offsetof(ZMMReg, ZMM_Q(0))); 3907 tcg_gen_st_i64(zero, OP_PTR0, offsetof(ZMMReg, ZMM_Q(1))); 3908 tcg_gen_st_i64(s->tmp1_i64, OP_PTR0, offsetof(ZMMReg, ZMM_Q(0)));
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/qemu/target/i386/nvmm/ |
H A D | nvmm-all.c | 163 &env->xmm_regs[i].ZMM_Q(0), 8); in nvmm_set_registers() 165 &env->xmm_regs[i].ZMM_Q(1), 8); in nvmm_set_registers() 317 memcpy(&env->xmm_regs[i].ZMM_Q(0), in nvmm_get_registers() 319 memcpy(&env->xmm_regs[i].ZMM_Q(1), in nvmm_get_registers()
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/qemu/target/i386/whpx/ |
H A D | whpx-all.c | 473 vcxt.values[idx].Reg128.Low64 = env->xmm_regs[i].ZMM_Q(0); in whpx_set_registers() 474 vcxt.values[idx].Reg128.High64 = env->xmm_regs[i].ZMM_Q(1); in whpx_set_registers() 700 env->xmm_regs[i].ZMM_Q(0) = vcxt.values[idx].Reg128.Low64; in whpx_get_registers() 701 env->xmm_regs[i].ZMM_Q(1) = vcxt.values[idx].Reg128.High64; in whpx_get_registers()
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