/qemu/tests/qtest/ |
H A D | tpm-tis-util.c | 48 uint8_t access; in tpm_tis_test_check_localities() local 55 access = readb(TIS_REG(locty, TPM_TIS_REG_ACCESS)); in tpm_tis_test_check_localities() 78 uint8_t access; in tpm_tis_test_check_access_reg() local 82 access = readb(TIS_REG(locty, TPM_TIS_REG_ACCESS)); in tpm_tis_test_check_access_reg() 109 uint8_t access; in tpm_tis_test_check_access_reg_seize() local 255 access = readb(TIS_REG(l, TPM_TIS_REG_ACCESS)); in tpm_tis_test_check_access_reg_seize() 263 access = readb(TIS_REG(l, TPM_TIS_REG_ACCESS)); in tpm_tis_test_check_access_reg_seize() 302 uint8_t access; in tpm_tis_test_check_access_reg_release() local 377 uint8_t access; in tpm_tis_test_check_transmit() local 384 access = readb(TIS_REG(0, TPM_TIS_REG_ACCESS)); in tpm_tis_test_check_transmit() [all …]
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H A D | tpm-tis-i2c-test.c | 94 uint8_t access; in tpm_tis_i2c_test_basic() local 103 access = tpm_tis_i2c_readb(0, TPM_I2C_REG_ACCESS); in tpm_tis_i2c_test_basic() 163 uint8_t access; in tpm_tis_i2c_test_check_localities() local 198 uint8_t access; in tpm_tis_i2c_test_check_access_reg() local 230 uint8_t access; in tpm_tis_i2c_test_check_access_reg_seize() local 381 access = tpm_tis_i2c_readb(l, TPM_I2C_REG_ACCESS); in tpm_tis_i2c_test_check_access_reg_seize() 389 access = tpm_tis_i2c_readb(l, TPM_I2C_REG_ACCESS); in tpm_tis_i2c_test_check_access_reg_seize() 428 uint8_t access; in tpm_tis_i2c_test_check_access_reg_release() local 505 uint8_t access; in tpm_tis_i2c_test_check_transmit() local 521 access = tpm_tis_i2c_readb(0, TPM_I2C_REG_ACCESS); in tpm_tis_i2c_test_check_transmit() [all …]
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/qemu/target/arm/ |
H A D | cortex-regs.c | 32 .access = PL1_RW, .readfn = l2ctlr_read, 36 .access = PL1_RW, .readfn = l2ctlr_read, 40 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 43 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 46 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 49 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 52 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 55 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 58 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 61 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, [all …]
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H A D | helper.c | 2112 .access = PL0_RW, 2253 .access = PL1_R, 2259 .access = PL1_RW, 2444 .access = PL0_RW, 2448 .access = PL0_RW, 2467 .access = PL1_RW, 2471 .access = PL1_RW, 5632 .access = PL0_W, 6507 .access = PL2_W, 6510 .access = PL2_W, [all …]
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H A D | debug_helper.c | 949 .access = PL0_R, .accessfn = access_tdra, 953 .access = PL1_R, .accessfn = access_tdra, 956 .access = PL0_R, .accessfn = access_tdra, 961 .access = PL1_RW, .accessfn = access_tda, 972 .access = PL0_R, .accessfn = access_tdcc, 1000 .access = PL1_RW, .accessfn = access_tda, 1011 .access = PL1_R, .accessfn = access_tda, 1015 .access = PL1_W, .type = ARM_CP_NO_RAW, 1021 .access = PL1_R, .resetvalue = 10, 1038 .access = PL1_RW, .accessfn = access_tda, [all …]
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/qemu/target/xtensa/ |
H A D | mmu_helper.c | 320 unsigned access; in xtensa_cpu_get_phys_page_debug() local 574 unsigned access = 0; in mmu_attr_to_access() local 577 access |= PAGE_READ; in mmu_attr_to_access() 579 access |= PAGE_EXEC; in mmu_attr_to_access() 582 access |= PAGE_WRITE; in mmu_attr_to_access() 601 return access; in mmu_attr_to_access() 620 return access[attr & 0xf]; in region_attr_to_access() 638 return access[attr & 0xf]; in cacheattr_attr_to_access() 788 return access & PAGE_READ; in is_access_granted() 794 return access & PAGE_EXEC; in is_access_granted() [all …]
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H A D | op_helper.c | 82 uint32_t paddr, page_size, access; in HELPER() local 85 xtensa_get_cring(env), &paddr, &page_size, &access); in HELPER() 92 (access & (PAGE_READ | PAGE_WRITE)) != (PAGE_READ | PAGE_WRITE)) { in HELPER() 106 access = PAGE_CACHE_BYPASS; in HELPER() 109 switch (access & PAGE_CACHE_MASK) { in HELPER() 136 uint32_t paddr, page_size, access; in HELPER() local 140 &page_size, &access); in HELPER() 148 access = PAGE_CACHE_BYPASS; in HELPER() 151 switch (access & PAGE_CACHE_MASK) { in HELPER()
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/qemu/docs/specs/ |
H A D | acpi_pci_hotplug.rst | 7 ACPI GPE block (IO ports 0xafe0-0xafe3, byte access) 13 PCI slot injection notification pending (IO port 0xae00-0xae03, 4-byte access) 21 PCI slot removal notification (IO port 0xae04-0xae07, 4-byte access) 29 PCI device eject (IO port 0xae08-0xae0b, 4-byte access) 38 - Read-only "up" register @0xae00, 4-byte access, bit per slot 39 - Read-only "down" register @0xae04, 4-byte access, bit per slot 40 - Read/write "eject" register @0xae08, 4-byte access, 42 - Read-only hotplug capable register @0xae0c, 4-byte access, bit per slot 44 PCI removability status (IO port 0xae0c-0xae0f, 4-byte access)
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H A D | acpi_cpu_hotplug.rst | 16 - ICH9-LPC (IO port 0x0cd8-0xcf7, 1-byte access) 17 - PIIX-PM (IO port 0xaf00-0xaf1f, 1-byte access) 54 Read access behavior 58 Command data 2: (DWORD access) 70 CPU device status fields: (1 byte access) 95 Command data: (DWORD access) 107 Write access behavior 111 CPU selector: (DWORD access) 118 CPU device control fields: (1 byte access) 146 Command field: (1 byte access) [all …]
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/qemu/target/arm/tcg/ |
H A D | cpu32.c | 170 .access = PL1_RW, in arm1026_initfn() 361 .access = PL1_RW, .resetvalue = 0, 364 .access = PL1_RW, .resetvalue = 0, 367 .access = PL1_RW, .resetvalue = 0, 373 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 375 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 550 .access = PL1_RW, .type = ARM_CP_CONST }, 552 .access = PL1_RW, .type = ARM_CP_CONST }, 554 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, 673 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 }, [all …]
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H A D | cpu64.c | 493 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 510 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 514 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 518 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 545 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 549 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 553 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 557 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 569 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 759 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, [all …]
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/qemu/pc-bios/optionrom/ |
H A D | optrom_fw_cfg.h | 54 struct fw_cfg_dma_access access; in bios_cfg_read_entry_dma() local 58 access.address = cpu_to_be64((uint64_t)(uint32_t)buf); in bios_cfg_read_entry_dma() 59 access.length = cpu_to_be32(len); in bios_cfg_read_entry_dma() 60 access.control = cpu_to_be32(control); in bios_cfg_read_entry_dma() 64 outl(cpu_to_be32((uint32_t)&access), BIOS_CFG_DMA_ADDR_LOW); in bios_cfg_read_entry_dma() 66 while (be32_to_cpu(access.control) & ~FW_CFG_DMA_CTL_ERROR) { in bios_cfg_read_entry_dma()
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/qemu/hw/core/ |
H A D | register.c | 79 ac = reg->access; in register_write() 100 prefix, reg->access->name, val, ac->unimp); in register_write() 134 ac = reg->access; in register_read() 166 if (!reg->data || !reg->access) { in register_reset() 170 ac = reg->access; in register_reset() 172 register_write_val(reg, reg->access->reset); in register_reset() 175 ac->post_write(reg, reg->access->reset); in register_reset() 188 if (reg_array->r[i]->access->addr == addr) { in register_write_memory() 217 if (reg_array->r[i]->access->addr == addr) { in register_read_memory() 267 r->access = &rae[i]; in register_init_block()
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/qemu/hw/tpm/ |
H A D | tpm_tis_common.c | 130 if ((s->loc[l].access & TPM_TIS_ACCESS_REQUEST_USE)) { in tpm_tis_check_request_use_except() 155 s->loc[s->active_locty].access &= mask; in tpm_tis_new_active_locality() 353 val = s->loc[locty].access & ~TPM_TIS_ACCESS_SEIZE; in tpm_tis_mmio_read() 539 s->loc[locty].access &= ~TPM_TIS_ACCESS_REQUEST_USE; in tpm_tis_mmio_write() 544 s->loc[locty].access &= ~TPM_TIS_ACCESS_BEEN_SEIZED; in tpm_tis_mmio_write() 561 if ((s->loc[locty].access & TPM_TIS_ACCESS_SEIZE)) { in tpm_tis_mmio_write() 567 if ((s->loc[l].access & TPM_TIS_ACCESS_SEIZE)) { in tpm_tis_mmio_write() 579 s->loc[l].access &= ~TPM_TIS_ACCESS_SEIZE; in tpm_tis_mmio_write() 582 s->loc[locty].access |= TPM_TIS_ACCESS_SEIZE; in tpm_tis_mmio_write() 834 s->loc[c].access = TPM_TIS_ACCESS_TPM_REG_VALID_STS; in tpm_tis_reset() [all …]
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/qemu/hw/intc/ |
H A D | arm_gicv3_cpuif.c | 2579 .access = PL1_RW, 2607 .access = PL2_RW, 2616 .access = PL3_RW, 2623 .access = PL3_RW, 2632 .access = PL3_RW, 2907 .access = PL2_RW, 2915 .access = PL2_RW, 2930 .access = PL2_R, 2936 .access = PL2_R, 2942 .access = PL2_R, [all …]
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/qemu/hw/i386/ |
H A D | vapic.c | 85 TPRAccess access; member 94 .access = TPR_ACCESS_READ, 100 .access = TPR_ACCESS_WRITE, 107 .access = TPR_ACCESS_WRITE, 114 .access = TPR_ACCESS_READ, 122 .access = TPR_ACCESS_READ, 130 .access = TPR_ACCESS_WRITE, 203 target_ulong *pip, TPRAccess access) in evaluate_tpr_instruction() argument 238 if (instr->access != access) { in evaluate_tpr_instruction() 468 TPRAccess access) in vapic_report_tpr_access() argument [all …]
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/qemu/hw/timer/ |
H A D | i8254.c | 130 int channel, access; in pit_ioport_write() local 159 access = (val >> 4) & 3; in pit_ioport_write() 160 if (access == 0) { in pit_ioport_write() 163 s->rw_mode = access; in pit_ioport_write() 164 s->read_state = access; in pit_ioport_write() 165 s->write_state = access; in pit_ioport_write()
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/qemu/docs/system/ |
H A D | security.rst | 74 malicious guest must not gain control of other guests or access their data. 81 The principle of least privilege states that each component only has access to 83 each process only has access to resources belonging to the guest. 85 The QEMU process should not have access to any resources that are inaccessible 87 QEMU process since it already has access to those same resources from within 91 requirements. For example, guest A only has access to its own disk image file 114 root to give it access to host devices (e.g. ``/dev/net/tun``) but this poses a 116 unprivileged QEMU process access to host devices without running QEMU as root. 118 for access to ``/dev/kvm``, ``/dev/net/tun``, and other device nodes. 148 commands exposed will instruct QEMU to access content on the host file system
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H A D | authz.rst | 7 authentication, access will be granted if the client successfully proves 11 access control. In this case QEMU provides a flexible system for enforcing 35 still not sufficiently strong access control the Distinguished Name of 60 This authorization driver provides a simple mechanism for granting access 62 known that only a single client is to be allowed access. 95 In some network backends it will be desirable to grant access to a range of 97 access by matching identities against a list of permitted one. Each match 130 access control policy by storing the match rules in a standalone file
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/qemu/docs/sphinx/ |
H A D | dbusparser.py | 64 def __init__(self, name, signature, access): argument 67 self.access = access 73 if self.access == "readwrite": 76 elif self.access == "read": 78 elif self.access == "write": 81 raise ValueError('Invalid access type "{}"'.format(self.access))
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H A D | dbusdomain.py | 213 access = None 215 access = _("read-only") 217 access = _("write-only") 219 access = _("read & write") 220 if access: 221 content = nodes.Text(access)
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/qemu/tests/avocado/ |
H A D | tcg_plugins.py | 84 mmap.mmap(lf.fileno(), 0, access=mmap.ACCESS_READ) as s: 115 mmap.mmap(lf.fileno(), 0, access=mmap.ACCESS_READ) as s: 145 mmap.mmap(lf.fileno(), 0, access=mmap.ACCESS_READ) as s:
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H A D | acpi-bits.py | 67 if os.path.exists(p) and os.access(p, os.X_OK): 178 self.assertTrue(os.access(os.path.join(bits_config_dir, 214 if os.access(os.path.join(target_test_dir, testfile_pyc), 258 self.assertTrue(os.access(mkrescue_script, 279 self.assertTrue(os.access(iso_file, os.R_OK)) 374 self.assertTrue(os.access(iso_file, os.R_OK))
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/qemu/system/ |
H A D | datadir.c | 40 if (access(name, R_OK) == 0) { in qemu_find_file() 58 if (access(buf, R_OK) == 0) { in qemu_find_file()
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/qemu/hw/net/fsl_etsec/ |
H A D | etsec.c | 90 switch (reg->access) { in etsec_read() 262 switch (reg->access) { in etsec_write() 322 etsec->regs[i].access = ACC_UNKNOWN; in etsec_reset() 333 etsec->regs[reg_index].access = eTSEC_registers_def[i].access; in etsec_reset()
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